MPC5200B Users Guide, Rev. 1
7-44 Freescale Semiconductor
General Purpose I/O (GPIO)
7.3.2.1.13 GPS GPIO Simple Interrupt Interrupt Enable Register —MBAR + 0x0B30
Bit Name Description
0:7 SIDVO Individual bits to control the state of pins configured as GPIO output.
bit 0 controls GPIO_SINT_7 (ETH_16 pin)
bit 1 controls GPIO_SINT_6 (ETH_15 pin)
bit 2 controls GPIO_SINT_5 (ETH_14 pin)
bit 3 controls GPIO_SINT_4 (ETH_13 pin)
bit 4 controls GPIO_SINT_3 (USB1_9 pin)
bit 5 controls GPIO_SINT_2 (PSC3_8 pin)
bit 6 controls GPIO_SINT_1 (PSC3_5 pin)
bit 7 controls GPIO_SINT_0 (PSC3_4 pin)
0 = Drive 0 on the pin (default)
1 = Drive 1 on the pin
8:31 — Reserved
Table 7-33. GPS GPIO Simple Interrupt Interrupt Enable Register
msb 012345678 9 101112131415
R SIINTEN
Reserved
W
RESET:0 00000000 0 0 0 00 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 lsb
R
Reserved
W
RESET:0 00000000 0 0 0 00 0 0
Bit Name Description
0:7 SIINTEN Individual bits to enable Interrupt generation for each GPIO pin configured as an Input.
bit 0 controls GPIO_SINT_7 (ETH_16 pin)
bit 1 controls GPIO_SINT_6 (ETH_15 pin)
bit 2 controls GPIO_SINT_5 (ETH_14 pin)
bit 3 controls GPIO_SINT_4 (ETH_13 pin)
bit 4 controls GPIO_SINT_3 (USB1_9 pin)
bit 5 controls GPIO_SINT_2 (PSC3_8 pin)
bit 6 controls GPIO_SINT_1 (PSC3_5 pin)
bit 7 controls GPIO_SINT_0 (PSC3_4 pin)
0 = Pin cannot generate an Interrupt (default)
1 = Pin can generate an Interrupt if configured as an Input GPIO
8:31 — Reserved
Note: See Interrupt Type data in GPS GPIO Simple Interrupt Interrupt Types Register —MBAR + 0x0B34 Register. Also,
the Master Interrupt Enable bit must be set in the GPS GPIO Simple Interrupt Master Enable Register —MBAR + 0x0B38
Register, before any Simple Interrupt pin can generate an Interrupt.
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