Freescale Semiconductor MPC5200B - FEC Receive Control Register-Mbar + 0 X3084

MPC5200B Users Guide, Rev. 1
14-20 Freescale Semiconductor
FEC Registers—MBAR + 0x3000
14.5.10 FEC Receive Control Register—MBAR + 0x3084
The R_CNTRL register is user programmable. It controls the operational mode of the receive block and should be written only when
ETHER_EN = 0 (initialization time).
Bits Name Description
0 MIB_DISABLE A read/write control bit. If set, MIB logic halts and MIB counters do not update.
1 MIB_IDLE A read-only status bit. If set, MIB block is not currently updating MIB counters.
2:31 — Reserved
Table 14-19. FEC Receive Control Register
msb 012345678 9 1011121314 15
R
Reserved MAX_FL
W
RESET:0 00001011 1 1 0 11 1 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 lsb
R
Reserved FCE
BC_REJ
PROM
MII_MODE
DRT LOOP
W
RESET:0 00000000 0 0 0 00 0 1
Bits Name Description
0:4 — Reserved
5:15 MAX_FL Maximum Frame Length—User R/W field. Resets to decimal 1518. The length is measured
starting at DA and includes CRC at End Of Frame (EOF). Tx frames longer than MAX_FL
causes the BABT interrupt to occur. Rx Frames longer than MAX_FL causes BABR interrupt
to occur and sets the EOF Receive Frame Status Word LG bit. The recommended user
programmed default value is 1518, or if VLAN Tags are supported, 1522.
16:25 — Reserved
26 FCE Flow Control Enable—If asserted, the receiver detects PAUSE frames. On PAUSE frame
detection, transmitter stops transmitting data frames for a given duration.
27 BC_REJ Broadcast Frame Reject—If asserted, frames with DA (destination address) =
FFFF_FFFF_FFFF are rejected, unless PROM bit is set. If both BC_REJ and PROM = 1,
frames with broadcast DA are accepted and M (MISS) bit is set in the Rx buffer descriptor.
28 PROM Promiscuous mode—All frames are accepted regardless of address matching.
29 MII_MODE Selects External Interface Mode—controls the interface mode for Tx/Rx blocks.
• Setting bit to 1 selects MII mode.
• Setting bit to 0 selects 7wire mode (used only for serial 10Mbps).