Freescale Semiconductor MPC5200B - PCI Controller Type 0 Configuration Space; General Control;Status Registers; Target Control Register PCITCR(RW) -MBAR + 0 X0 D6 C; PCI Arbiter Register PCIARB(RW) -MBAR + 0 X0 D8 C

MPC5200B Users Guide, Rev. 1
Freescale Semiconductor B-3
Section 9.7.2 SCLPC Registers—MBAR + 0x3C00 ....................................................................................................... 9-23
9.7.2.1 SCLPC Packet Size Register—MBAR + 0x3C00 ............................................................................... 9-23
9.7.2.2 SCLPC Start Address Register—MBAR + 0x3C04 ............................................................................ 9-24
9.7.2.3 SCLPC Control Register—MBAR + 0x3C08...................................................................................... 9-24
9.7.2.4 SCLPC Enable Register—MBAR + 0x3C0C ......................................................................................9-25
9.7.2.5 SCLPC Bytes Done Status Register—MBAR + 0x3C14..................................................................... 9-26
Section
9.7.3 SCLPC FIFO Registers—MBAR + 0x3C40.............................................................................................. 9-28
9.7.3.1 LPC Rx/Tx FIFO Data Word Register—MBAR + 0x3C40 ................................................................ 9-28
9.7.3.2 LPC Rx/Tx FIFO Status Register—MBAR + 0x3C44........................................................................ 9-29
9.7.3.3 LPC Rx/Tx FIFO Control Register—MBAR + 0x3C48 ..................................................................... 9-30
9.7.3.4 LPC Rx/Tx FIFO Alarm Register—MBAR + 0x3C4C ...................................................................... 9-30
9.7.3.5 LPC Rx/Tx FIFO Read Pointer Register—MBAR + 0x3C50............................................................. 9-31
9.7.3.6 LPC Rx/Tx FIFO Write Pointer Register—MBAR + 0x3C54............................................................ 9-31
Section
10.3.1 PCI Controller Type 0 Configuration Space .............................................................................................. 10-6
10.3.3.1.1 Tx Packet Size PCITPSR(RW) —MBAR + 0x3800.......................................................................... 10-24
10.3.3.1.2 Tx Start Address PCITSAR(RW) —MBAR + 0x3804...................................................................... 10-24
10.3.3.1.3 Tx Transaction Control Register PCITTCR(RW) —MBAR + 0x3808 ............................................. 10-24
10.3.3.1.4 Tx Enables PCITER(RW)—MBAR + 0x380C.................................................................................. 10-26
10.3.3.1.5 Tx Next Address PCITNAR(R) —MBAR + 0x3810......................................................................... 10-27
10.3.3.1.6 Tx Last Word PCITLWR(R) —MBAR + 0x3814.............................................................................. 10-28
10.3.3.1.7 Tx Bytes Done Counts PCITDCR(R) —MBAR + 0x3818 ............................................................... 10-28
10.3.3.1.8 Tx Packets Done Counts PCITPDCR(R) —MBAR + 0x3820 .......................................................... 10-28
10.3.3.1.9 Tx Status PCITSR(RWC) —MBAR + 0x381C ................................................................................. 10-29
10.3.3.1.10 Tx FIFO Data Register PCITFDR(RW) —MBAR + 0x3840............................................................ 10-30
10.3.3.1.11 Tx FIFO Status Register PCITFSR(R/RWC) —MBAR + 0x3844 .................................................... 10-31
10.3.3.1.12 Tx FIFO Control Register PCITFCR(RW) —MBAR + 0x3848 ....................................................... 10-32
10.3.3.1.13 Tx FIFO Alarm Register PCITFAR(RW) —MBAR + 0x384C......................................................... 10-32
10.3.3.1.14 Tx FIFO Read Pointer Register PCITFRPR(RW) —MBAR + 0x3850............................................. 10-34
10.3.3.1.15 Tx FIFO Write Pointer Register PCITFWPR(RW) —MBAR + 0x3854........................................... 10-34
Section
10.3.2 General Control/Status Registers ............................................................................................................. 10-13
10.3.2.1 Global Status/Control Register PCIGSCR(RW) —MBAR + 0x0D60............................................... 10-13
10.3.2.2 Target Base Address Translation Register 0 PCITBATR0(RW) —MBAR + 0x0D64 ...................... 10-16
10.3.2.3 Target Base Address Translation Register 1 PCITBATR1(RW) —MBAR + 0x0D68 ...................... 10-16
10.3.2.4 Target Control Register PCITCR(RW) —MBAR + 0x0D6C ............................................................ 10-17
10.3.2.5 Initiator Window 0 Base/Translation Address Register PCIIW0BTAR(RW)—MBAR + 0x0D70 ... 10-18
10.3.2.6 Initiator Window 1 Base/Translation Address Register PCIIW1BTAR(RW) —MBAR + 0x0D74 .. 10-19
10.3.2.7 Initiator Window 2 Base/Translation Address Register PCIIW2BTAR(RW) —MBAR + 0x0D78 .. 10-20
10.3.2.8 Initiator Window Configuration Register PCIIWCR(RW) —MBAR + 0x0D80............................... 10-20
10.3.2.9 Initiator Control Register PCIICR(RW) —MBAR + 0x0D84 ........................................................... 10-21
10.3.2.10 Initiator Status Register PCIISR(RWC) —MBAR + 0x0D88 ........................................................... 10-22
10.3.2.11 PCI Arbiter Register PCIARB(RW) —MBAR + 0x0D8C ................................................................ 10-22
10.3.2.12 Configuration Address Register PCICAR (RW) —MBAR + 0x0DF8 .............................................. 10-23
Section
10.3.3 Communication Sub-System Interface Registers..................................................................................... 10-23
10.3.3.1.1 Tx Packet Size PCITPSR(RW) —MBAR + 0x3800.......................................................................... 10-24
10.3.3.1.2 Tx Start Address PCITSAR(RW) —MBAR + 0x3804...................................................................... 10-24
10.3.3.1.3 Tx Transaction Control Register PCITTCR(RW) —MBAR + 0x3808 ............................................. 10-24
10.3.3.1.4 Tx Enables PCITER(RW)—MBAR + 0x380C.................................................................................. 10-26
10.3.3.1.5 Tx Next Address PCITNAR(R) —MBAR + 0x3810......................................................................... 10-27