MPC5200B Users Guide, Rev. 1
B-4 Freescale Semiconductor
10.3.3.1.6 Tx Last Word PCITLWR(R) —MBAR + 0x3814.............................................................................. 10-28
10.3.3.1.7 Tx Bytes Done Counts PCITDCR(R) —MBAR + 0x3818 ............................................................... 10-28
10.3.3.1.8 Tx Packets Done Counts PCITPDCR(R) —MBAR + 0x3820 .......................................................... 10-28
10.3.3.1.9 Tx Status PCITSR(RWC) —MBAR + 0x381C ................................................................................. 10-29
10.3.3.1.10 Tx FIFO Data Register PCITFDR(RW) —MBAR + 0x3840............................................................ 10-30
10.3.3.1.11 Tx FIFO Status Register PCITFSR(R/RWC) —MBAR + 0x3844 .................................................... 10-31
10.3.3.1.12 Tx FIFO Control Register PCITFCR(RW) —MBAR + 0x3848 ....................................................... 10-32
10.3.3.1.13 Tx FIFO Alarm Register PCITFAR(RW) —MBAR + 0x384C......................................................... 10-32
10.3.3.1.14 Tx FIFO Read Pointer Register PCITFRPR(RW) —MBAR + 0x3850............................................. 10-34
10.3.3.2.15 Rx FIFO Write Pointer Register PCIRFWPR (RW) —MBAR + 0x38D4......................................... 10-44
Section
10.3.3.2 Multi-Channel DMA Receive Interface ................................................................................................... 10-34
10.3.3.2.1 Rx Packet Size PCIRPSR(RW) —MBAR + 0x3880 ......................................................................... 10-35
10.3.3.2.2 Rx Start Address PCIRSAR (RW) —MBAR + 0x3884 .................................................................... 10-35
10.3.3.2.3 Rx Transaction Control Register PCIRTCR(RW) —MBAR + 0x3888 ............................................. 10-35
10.3.3.2.4 Rx Enables PCIRER (RW) —MBAR + 0x388C ............................................................................... 10-37
10.3.3.2.5 Rx Next Address PCIRNAR(R) —MBAR + 0x3890 ........................................................................ 10-38
10.3.3.2.6 Rx Last Word PCIRLWR(R) —MBAR + 0x3894 ............................................................................. 10-38
10.3.3.2.7 Rx Bytes Done Counts PCIRDCR(R) —MBAR + 0x3898 ............................................................... 10-39
10.3.3.2.8 Rx Packets Done Counts PCIRPDCR(R) —MBAR + 0x38A0......................................................... 10-39
10.3.3.2.9 Rx Status PCIRSR (R/sw1) —MBAR + 0x389C............................................................................... 10-40
10.3.3.2.10 Rx FIFO Data Register PCIRFDR(RW) —MBAR + 0x38C0........................................................... 10-41
10.3.3.2.11 Rx FIFO Status Register PCIRFSR(R/sw1) —MBAR + 0x38C4 ..................................................... 10-41
10.3.3.2.12 Rx FIFO Control Register PCIRFCR(RW) —MBAR + 0x38C8 ...................................................... 10-42
10.3.3.2.13 Rx FIFO Alarm Register PCIRFAR(RW) —MBAR + 0x38CC........................................................ 10-43
10.3.3.2.14 Rx FIFO Read Pointer Register PCIRFRPR(RW) —MBAR + 0x38D0 ........................................... 10-44
10.3.3.2.15 Rx FIFO Write Pointer Register PCIRFWPR (RW) —MBAR + 0x38D4......................................... 10-44
Section
11.3.1 ATA Host Registers—MBAR + 0x3A00 ....................................................................................................11-2
11.3.1.1 ATA Host Configuration Register—MBAR + 0x3A00.........................................................................11-2
11.3.1.2 ATA Host Status Register—MBAR + 0x3A04 .....................................................................................11-3
11.3.1.3 ATA PIO Timing 1 Register—MBAR + 0x3A08..................................................................................11-3
11.3.1.4 ATA PIO Timing 2 Register—MBAR + 0x3A0C.................................................................................11-4
11.3.1.5 ATA Multiword DMA Timing 1 Register—MBAR + 0x3A10.............................................................11-4
11.3.1.6 ATA Multiword DMA Timing 2 Register—MBAR + 0x3A14.............................................................11-5
11.3.1.7 ATA Ultra DMA Timing 1 Register—MBAR + 0x3A18 .....................................................................11-5
11.3.1.8 ATA Ultra DMA Timing 2 Register—MBAR + 0x3A1C.....................................................................11-6
11.3.1.9 ATA Ultra DMA Timing 3 Register—MBAR + 0x3A20 .....................................................................11-6
11.3.1.10 ATA Ultra DMA Timing 4 Register—MBAR + 0x3A24 .....................................................................11-7
11.3.1.11 ATA Ultra DMA Timing 5 Register—MBAR + 0x3A28 .....................................................................11-8
11.3.1.12 ATA Share Count Register—MBAR + 0x3A2C ...................................................................................11-8
Section
11.3.2 ATA FIFO Registers—MBAR + 0x3A00 ...................................................................................................11-8
11.3.2.1 ATA Rx/Tx FIFO Data Word Register—MBAR + 0x3A3C ................................................................11-9
11.3.2.2 ATA Rx/Tx FIFO Status Register—MBAR + 0x3A40 ........................................................................11-9
11.3.2.3 ATA Rx/Tx FIFO Control Register—MBAR + 0x3A44....................................................................11-10
11.3.2.4 ATA Rx/Tx FIFO Alarm Register—MBAR + 0x3A48......................................................................11-10
11.3.2.5 ATA Rx/Tx FIFO Read Pointer Register—MBAR + 0x3A4C...........................................................11-11
11.3.2.6 ATA Rx/Tx FIFO Write Pointer Register—MBAR + 0x3A50...........................................................11-11
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