MPC5200B Users Guide, Rev. 1
Freescale Semiconductor B-5
Section 11.3.3 ATA Drive Registers—MBAR + 0x3A00.................................................................................................11-12
11.3.3.1 ATA Drive Device Control Register—MBAR + 0x3A5C ..................................................................11-12
11.3.3.2 ATA Drive Alternate Status Register—MBAR + 0x3A5C .................................................................11-13
11.3.3.3 ATA Drive Data Register—MBAR + 0x3A60 ....................................................................................11-13
11.3.3.4 ATA Drive Features Register—MBAR + 0x3A64 ..............................................................................11-14
11.3.3.5 ATA Drive Error Register—MBAR + 0x3A64 ...................................................................................11-14
11.3.3.6 ATA Drive Sector Count Register—MBAR + 0x3A68 ......................................................................11-15
11.3.3.7 ATA Drive Sector Number Register—MBAR + 0x3A6C ..................................................................11-15
11.3.3.8 ATA Drive Cylinder Low Register—MBAR + 0x3A70 .....................................................................11-16
11.3.3.9 ATA Drive Cylinder High Register—MBAR + 0x3A74 ....................................................................11-16
11.3.3.10 ATA Drive Device/Head Register—MBAR + 0x3A78......................................................................11-17
11.3.3.11 ATA Drive Device Command Register—MBAR + 0x3A7C..............................................................11-17
11.3.3.12 ATA Drive Device Status Register—MBAR + 0x3A7C.....................................................................11-19
Section
12.4.2 Control and Status Partition—MBAR + 0x1000........................................................................................ 12-6
12.4.2.1 USB HC Revision Register—MBAR + 0x1000 .................................................................................. 12-6
12.4.2.2 USB HC Control Register—MBAR + 0x1004 .................................................................................... 12-6
12.4.2.3 USB HC Command Status Register—MBAR + 0x1008..................................................................... 12-8
12.4.2.4 USB HC Interrupt Status Register —MBAR + 0x100C...................................................................... 12-9
12.4.2.5 USB HC Interrupt Enable Register—MBAR + 0x1010.................................................................... 12-10
12.4.2.6 USB HC Interrupt Disable Register—MBAR + 0x1014 ....................................................................12-11
Section
12.4.3 Memory Pointer Partition—MBAR + 0x1018......................................................................................... 12-12
12.4.3.1 USB HC HCCA Register—MBAR + 0x1018 ................................................................................... 12-13
12.4.3.2 USB HC Period Current Endpoint Descriptor Register —MBAR + 0x101C.................................... 12-13
12.4.3.3 USB HC Control Head Endpoint Descriptor Register —MBAR + 0x1020 ...................................... 12-14
12.4.3.4 USB HC Control Current Endpoint Descriptor Register —MBAR + 0x1024................................... 12-14
12.4.3.5 USB HC Bulk Head Endpoint Descriptor Register—MBAR + 0x1028............................................ 12-14
12.4.3.6 USB HC Bulk Current Endpoint Descriptor Register—MBAR + 0x102C ....................................... 12-15
12.4.3.7 USB HC Done Head Register—MBAR + 0x1030............................................................................. 12-15
Section 12.4.4 Frame Counter Partition—MBAR + 0x1034 ........................................................................................... 12-16
12.4.4.1 USB HC Frame Interval Register—MBAR + 0x1034 ....................................................................... 12-16
12.4.4.2 USB HC Frame Remaining Register—MBAR + 0x1038.................................................................. 12-17
12.4.4.3 USB HC Frame Number Register—MBAR + 0x103C...................................................................... 12-17
12.4.4.4 USB HC Periodic Start Register—MBAR + 0x1040......................................................................... 12-18
12.4.4.5 USB HC LS Threshold Register—MBAR + 0x1044......................................................................... 12-18
Section
12.4.5 Root Hub Partition—MBAR + 0x1048.................................................................................................... 12-19
12.4.5.1 USB HC Rh Descriptor A Register—MBAR + 0x1048 .................................................................... 12-19
12.4.5.2 USB HC Rh Descriptor B Register—MBAR + 0x104C.................................................................... 12-20
12.4.5.3 USB HC Rh Status Register—MBAR + 0x1050 ............................................................................... 12-21
12.4.5.4 USB HC Rh Port1 Status Register—MBAR + 0x1054...................................................................... 12-22
12.4.5.5 USB HC Rh Port2 Status Register—MBAR + 0x1058...................................................................... 12-26
Section
13.2 BestComm Functional Description ............................................................................................................ 13-1
13.15.1 SDMA Task Bar Register—MBAR + 0x1200 ..................................................................................... 13-4
13.15.2 SDMA Current Pointer Register—MBAR + 0x1204........................................................................... 13-5
13.15.3 SDMA End Pointer Register—MBAR + 0x1208 ................................................................................ 13-5
13.15.4 SDMA Variable Pointer Register—MBAR + 0x120C......................................................................... 13-5
13.15.5 SDMA Interrupt Vector, PTD Control Register—MBAR + 0x1210.................................................... 13-6
13.15.6 SDMA Interrupt Pending Register—MBAR + 0x1214 ....................................................................... 13-7
13.15.7 SDMA Interrupt Mask Register—MBAR + 0x1218............................................................................ 13-8
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