Freescale Semiconductor MPC5200B - External Signals; Features

List of Tables
Table Page
Number Number
MPC5200B Users Guide, Rev. 1
LOT-4 Freescale Semiconductor
10-9 Special Cycle Message Encodings ........................................................................................................................10-54
10-10 Unsupported XLB Transfers .................................................................................................................................10-54
10-11 Aligned PCI to XL bus Transfers ..........................................................................................................................10-55
10-12 Non-contiguous PCI to XL bus Transfers (require two XLB bus accesses) .........................................................10-56
10-13 Comm bus to PCI Byte Lanes for Memory Transactions .....................................................................................10-57
10-14 XLB:IP:PCI Clock Ratios .....................................................................................................................................10-59
10-15 Transaction Mapping: XLB -> PCI .......................................................................................................................10-60
11-1 ATA Host Configuration Register ..........................................................................................................................11-2
11-2 ATA Host Status Register .......................................................................................................................................11-3
11-3 ATA PIO Timing 1 Register ...................................................................................................................................11-3
11-4 ATA PIO Timing 2 Register ...................................................................................................................................11-4
11-5 ATA Multiword DMA Timing 1 Register ..............................................................................................................11-4
11-6 ATA Multiword DMA Timing 2 Register ..............................................................................................................11-5
11-7 ATA Ultra DMA Timing 1 Register .......................................................................................................................11-5
11-8 ATA Ultra DMA Timing 2 Register .......................................................................................................................11-6
11-9 ATA Ultra DMA Timing 3 Register .......................................................................................................................11-6
11-10 ATA Ultra DMA Timing 4 Register .......................................................................................................................11-7
11-11 ATA Ultra DMA Timing 5 Register .......................................................................................................................11-8
11-12 ata_shre_cnt .............................................................................................................................................................11-8
11-13 ATA Rx/Tx FIFO Data Word Register ..................................................................................................................11-9
11-14 ATA Rx/Tx FIFO Status Register ..........................................................................................................................11-9
11-15 ATA Rx/Tx FIFO Control Register ......................................................................................................................11-10
11-16 ATA Rx/Tx FIFO Alarm Register ........................................................................................................................11-10
11-17 ATA Rx/Tx FIFO Read Pointer Register .............................................................................................................11-11
11-18 ATA Rx/Tx FIFO Write Pointer Register ............................................................................................................11-11
11-19 ATA Drive Device Control Register .....................................................................................................................11-12
11-20 ATA Drive Alternate Status Register ....................................................................................................................11-13
11-21 ATA Drive Data Register ......................................................................................................................................11-13
11-22 ATA Drive Features Register ................................................................................................................................11-14
11-23 ATA Drive Error Register .....................................................................................................................................11-14
11-24 ATA Drive Sector Count Register ........................................................................................................................11-15
11-25 ATA Drive Sector Number Register .....................................................................................................................11-15
11-26 ATA Drive Cylinder Low Register .......................................................................................................................11-16
11-27 ATA Drive Cylinder High Register ......................................................................................................................11-16
11-28 ATA Drive Device/Head Register ........................................................................................................................11-17
11-29 ATA Drive Device Command Register ................................................................................................................11-17
11-30 ATA Drive Device Status Register .......................................................................................................................11-19
11-31 PIO Timing Requirements .....................................................................................................................................11-21
11-23 Multiword DMA Timing Requirements ................................................................................................................11-22
11-33 MPC5200 External Signals .................................................................................................
..................................11-23
11-34 ATA Controller External Connections ..................................................................................................................11-24
11-35 ATA Standards ......................................................................................................................................................11-27
11-36 ATA Physical Level Modes ..................................................................................................................................11-27
11-37 ATA Register Address/Chip Select Decoding .....................................................................................................11-28
11-38 DMA Command Parameters .................................................................................................................................11-33
11-39 Redefinition of Signal Lines for Ultra DMA Protocol ..........................................................................................11-36
11-40 Reset Timing Characteristics .................................................................................................................................11-37
12-1 USB HC Revision Register .....................................................................................................................................12-6
12-2 USB HC Control Register .......................................................................................................................................12-6
12-3 USB HC Command Status Register ........................................................................................................................12-8
12-4 USB HC Interrupt Status Register ...........................................................................................................................12-9
12-5 USB HC Interrupt Enable Register .......................................................................................................................12-10
12-6 USB HC Interrupt Disable Register ......................................................................................................................12-11
12-7 USB HC HCCA Register ......................................................................................................................................12-13