List of Tables
Table Page
Number Number
MPC5200B Users Guide, Rev. 1
Freescale Semiconductor LOT-3
7-51 SLT 0 Terminal Count Register ..............................................................................................................................7-62
7-52 SLT 0 Control Register ...........................................................................................................................................7-62
7-53 SLT 0 Count Value Register ...................................................................................................................................7-63
7-54 SLT 0 Timer Status Register ...................................................................................................................................7-64
7-55 Real-Time Clock Signals .........................................................................................................................................7-65
7-56 RTC Time Set Register ...........................................................................................................................................7-66
7-57 RTC Date Set Register ............................................................................................................................................7-67
7-58 RTC New Year and Stopwatch Register .................................................................................................................7-68
7-59 RTC Alarm and Interrupt Enable Register ..............................................................................................................7-68
7-60 RTC Current Time Register ....................................................................................................................................7-69
7-61 RTC Current Date Register .....................................................................................................................................7-70
7-62 RTC Alarm and Stopwatch Interrupt Register ........................................................................................................7-70
7-63 RTC Periodic Interrupt and Bus Error Register ......................................................................................................7-71
7-64 RTC Test Register/Divides Register .......................................................................................................................7-72
8-1 Legal Memory Configurations ..................................................................................................................................8-4
8-2 SDRAM External Signals .......................................................................................................................................8-11
8-3 SDRAM Commands ................................................................................................................................................8-13
8-4 Memory Controller Mode Register .........................................................................................................................8-18
8-5 Memory Controller Control Register ......................................................................................................................8-19
8-6 High Address Usage ................................................................................................................................................8-20
8-7 SDRAM Address Multiplexing ...............................................................................................................................8-20
8-8 Memory Controller Configuration Register 1 .........................................................................................................8-22
8-9 Memory Controller Configuration Register 2 .........................................................................................................8-23
9-1 LocalPlus External Signals ........................................................................................................................................9-2
9-2 Non-Muxed Mode Options .......................................................................................................................................9-4
9-3 Non-Muxed Aligned Data Transfers .........................................................................................................................9-5
9-4 MUXed Mode Options ..............................................................................................................................................9-6
9-5 Non-Muxed Aligned Data Transfers .........................................................................................................................9-8
9-6 BOOT_CONFIG (RST_CONFIG) Options ............................................................................................................9-11
9-7 Chip Select 0/Boot Configuration Register .............................................................................................................9-13
9-8 Chip Select 1 Configuration Register ......................................................................................................................9-15
9-9 Chip Select Control Register ...................................................................................................................................9-17
9-10 Chip Select Status Register .....................................................................................................................................9-18
9-11 Chip Select Burst Control Register .........................................................................................................................9-19
9-12 Chip Select Deadcycle Control Register .................................................................................................................9-22
9-13 SCLPC Packet Size Register ...................................................................................................................................9-23
9-14 SCLPC Start Address Register ................................................................................................................................9-24
9-15 SCLPC Control Register .........................................................................................................................................9-25
9-16 SCLPC Enable Register ..........................................................................................................................................9-26
9-17 SCLPC Bytes Done Status Register ........................................................................................................................9-27
9-18 LPC Rx/Tx FIFO Data Word Register ...................................................................................................................9-28
9-19 LPC Rx/Tx FIFO Status Register ...........................................................................................................................9-28
9-20 LPC Rx/Tx FIFO Control Register .........................................................................................................................9-29
9-21 LPC Rx/Tx FIFO Alarm Register ...........................................................................................................................9-30
9-22 LPC Rx/Tx FIFO Read Pointer Register ................................................................................................................9-30
9-23 LPC Rx/Tx FIFO Write Pointer Register ...............................................................................................................9-31
10-1 PCI External Signals ...............................................................................................................................................10-2
10-2 PCI Register Map ....................................................................................................................................................10-4
10-3 PCI Communication System Interface Register Map .............................................................................................10-5
10-4 PCI Command encoding .......................................................................................................................................10-42
10-5 PCI Bus Commands ..............................................................................................................................................10-44
10-6 PCI I/O space byte decoding .................................................................................................................................10-46
10-7 XLB bus to PCI Byte Lanes for Memory Transactions .......................................................................................10-49
10-8 Type 0 Configuration Device Number to IDSEL Translation ..............................................................................10-52
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