Table of Contents
Paragraph Page
Number Number
MPC5200B Users Guide, Rev. 1
Freescale Semiconductor TOC-1
Chapter 1 Introduction
1.1 Overview ...................................................................................................................................................................1-1
1.1.1 Features ...............................................................................................................................................................1-1
1.2 Architecture ...............................................................................................................................................................1-2
1.2.1 Embedded G2_LE Core ......................................................................................................................................1-6
1.2.2 BestComm I/O Subsystem .................................................................................................................................1-7
1.2.2.1 Programmable Serial Controllers (PSCs) ....................................................................................................1-7
1.2.2.2 10/100 Ethernet Controller ..........................................................................................................................1-7
1.2.2.3 Universal Serial Bus (USB) .........................................................................................................................1-7
1.2.2.4 Infrared Support ............................................................................................................................................1-7
1.2.2.5 Inter-Integrated Circuit (I
2
C) ......................................................................................................................1-7
1.2.2.6 Serial Peripheral Interface (SPI) ..................................................................................................................1-7
1.2.3 Dual Freescale (formerly Motorola) Scalable (MS) Controller Area Network (CAN) .....................................1-7
1.2.4 Byte Data Link Controller - Digital BDLC-D ....................................................................................................1-8
1.2.5 System Level Interfaces ......................................................................................................................................1-8
1.2.5.1 Chip Selects ..................................................................................................................................................1-8
1.2.5.2 Interrupt Controller .......................................................................................................................................1-8
1.2.5.3 Timers ...........................................................................................................................................................1-8
1.2.5.4 General Purpose Input/Outputs (GPIO) ......................................................................................................1-8
1.2.5.5 Functional Pin Multiplexing .........................................................................................................................1-9
1.2.5.6 Real-Time Clock (RTC) ..............................................................................................................................1-9
1.2.6 SDRAM Controller and Interface .......................................................................................................................1-9
1.2.7 Multi-Function External LocalPlus Bus .............................................................................................................1-9
1.2.8 Power Management ............................................................................................................................................1-9
1.2.9 Systems Debug and Test ...................................................................................................................................1-10
1.2.10 Physical Characteristics ....................................................................................................................................1-10
Chapter 2 Signal Descriptions
2.1 Overview ...................................................................................................................................................................2-1
2.2 Pinout Tables .............................................................................................................................................................2-4
Chapter 3 Memory Map
3.1 Overview ...................................................................................................................................................................3-1
3.2 Internal Register Memory Map .................................................................................................................................3-2
3.3 MPC5200 Memory Map ...........................................................................................................................................3-3
3.3.1 MPC5200 Internal Register Space ......................................................................................................................3-3
3.3.2 External Busses ...................................................................................................................................................3-3
3.3.2.1 SDRAM Bus .................................................................................................................................................3-3
3.3.2.2 LocalPlus Bus ...............................................................................................................................................3-4
3.3.3 Memory Map Space Register Description ..........................................................................................................3-4
3.3.3.1 Memory Address Base Register —MBAR + 0x0000 ..................................................................................3-4
3.3.3.2 Boot and Chip Select Addresses ...................................................................................................................3-5
3.3.3.3 SDRAM Chip Select Configuration Registers .............................................................................................3-6
3.3.3.4 IPBI Control Register and Wait State Enable —MBAR+0x0054 ...............................................................3-7
Chapter 4 Resets and Reset Configuration
4.1 Overview ...................................................................................................................................................................4-1
4.2 Hard and Soft Reset Pins ...........................................................................................................................................4-1
4.2.1 Power-On Reset—PORESET .............................................................................................................................4-1
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