Freescale Semiconductor MPC5200B - Page 3

Table Of Contents
Paragraph Page
Number Number
MPC5200B Users Guide, Rev. 1
TOC-2 Freescale Semiconductor
4.2.2 Hard Reset—HRESET ........................................................................................................................................4-1
4.2.3 Soft Reset—SRESET ..........................................................................................................................................4-2
4.3 Reset Sequence ..........................................................................................................................................................4-2
4.4 Reset Operation .........................................................................................................................................................4-2
4.5 Other Resets ..............................................................................................................................................................4-3
4.6 Reset Configuration ...................................................................................................................................................4-4
Chapter 5 Clocks and Power Management
5.1 Overview ...................................................................................................................................................................5-1
5.2 Clock Distribution Module (CDM) ...........................................................................................................................5-1
5.3 MPC5200 Clock Domains .........................................................................................................................................5-1
5.3.1 MPC5200 Top Level Clock Relations ................................................................................................................5-3
5.3.2 603e G2_LE Core Clock Domain .......................................................................................................................5-5
5.3.3 Processor Bus (XLB ) Clock Domain .................................................................................................................5-7
5.3.4 SDRAM Memory Controller Clock Domain ......................................................................................................5-7
5.3.5 IPB Clock Domain ..............................................................................................................................................5-8
5.3.6 PCI Clock Domain ..............................................................................................................................................5-8
5.4 Power Management ...................................................................................................................................................5-9
5.4.1 Full-Power Mode ................................................................................................................................................5-9
5.4.2 Power Conservation Modes ................................................................................................................................5-9
5.4.3 603e G2_LE Core Power Modes ........................................................................................................................5-9
5.4.3.1 Dynamic Power Mode ................................................................................................................................5-10
5.4.3.2 Doze Mode .................................................................................................................................................5-10
5.4.3.3 Nap Mode ...................................................................................................................................................5-10
5.4.3.4 Sleep Mode .................................................................................................................................................5-10
5.4.4 Deep-Sleep Mode ..............................................................................................................................................5-10
5.4.4.1 Entering Deep Sleep ...................................................................................................................................5-11
5.4.4.2 Exiting Deep Sleep .....................................................................................................................................5-11
5.5 CDM Registers ........................................................................................................................................................5-11
5.5.1 CDM JTAG ID Number Register—MBAR + 0x0200 .....................................................................................5-12
5.5.2 CDM Power On Reset Configuration Register—MBAR + 0x0204 .................................................................5
-12
5.5.3 CDM Bread Crumb Register—MBAR + 0x0208 ............................................................................................5-14
5.5.4 CDM Configuration Register—MBAR + 0x020C ...........................................................................................5-14
5.5.5 CDM 48MHz Fractional Divider Configuration Register—MBAR + 0x0210 ................................................5-15
5.5.6 CDM Clock Enable Register—MBAR + 0x0214 ............................................................................................5-16
5.5.7 CDM System Oscillator Configuration Register—MBAR + 0x0218 ..............................................................5-17
5.5.8 CDM Clock Control Sequencer Configuration Register—MBAR + 0x021C ..................................................5-18
5.5.9 CDM Soft Reset Register—MBAR + 0x0220 ..................................................................................................5-19
5.5.10 CDM System PLL Status Register—MBAR + 0x0224 ...................................................................................5-19
5.5.11 PSC1 Mclock Config Register—MBAR + 0x0228 ..........................................................................................5-20
5.5.12 PSC2 Mclock Config Register—MBAR + 0x022C .........................................................................................5-21
5.5.13 PSC3 Mclock Config Register—MBAR + 0x0230 ..........................................................................................5-21
5.5.14 PSC6 (IrDA) Mclock Config Register—MBAR + 0x0234 ..............................................................................5-22
Chapter 6 G2_LE Processor Core
6.1 Overview ...................................................................................................................................................................6-1
6.2 MPC5200 G2_LE Processor Core Functional Overview ..........................................................................................6-1
6.3 G2_LE Core Reference Manual ................................................................................................................................6-2
6.4 Not supported G2_LE Core Feature ..........................................................................................................................6-2
6.4.1 Not supported instruction ....................................................................................................................................6-2
6.4.2 Not supported XLB parity feature ......................................................................................................................6-2