Freescale Semiconductor MPC5200B - ATA Ultra DMA Timing 2 Register-Mbar + 0 X3 A1 C; ATA Ultra DMA Timing 3 Register-Mbar + 0 X3 A20

MPC5200B Users Guide, Rev. 1
11-6 Freescale Semiconductor
ATA Register Interface
11.3.1.8 ATA Ultra DMA Timing 2 Register—MBAR + 0x3A1C
11.3.1.9 ATA Ultra DMA Timing 3 Register—MBAR + 0x3A20
Bits Name Description
0:7 udma_t2cyc Ultra DMA sustained average two cycle time. Count value is based on system clock
operating frequency.
8:15 udma_tcyc Ultra DMA strobe edge to strobe edge cycle time. Count value is based on system clock
operating frequency.
16:23 udma_tds Ultra DMA read data setup time. Count value is based on system clock operating
frequency.
24:31 udma_tdh Ultra DMA read data hold time. Count value is based on system clock operating frequency.
Table 11-8. ATA Ultra DMA Timing 2 Register
msb 012345678 9 1011121314 15
R udma_tdvs udma_tdvh
W
RESET:0 00000000 0 0 0 00 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 lsb
R udma_tfs udma_tli
W
RESET:0 00000000 0 0 0 00 0 0
Bits Name Description
0:7 udma_tdvs Ultra DMA write data setup time. Count value is based on system clock operating
frequency.
8:15 udma_tdvh Ultra DMA write data hold time. Count value is based on system clock operating frequency.
16:23 udma_tfs First strobe time during the initiation of ultra DMA data transfer. Count value is based on
system clock operating frequency.
24:31 udma_tli Limited interlock time with a defined maximum, when drive or host are waiting for response
from each other. Count value is based on system clock operating frequency.
Table 11-9. ATA Ultra DMA Timing 3 Register
msb 012345678 9 1011121314 15
R udma_tmli udma_taz
W
RESET:0 00000000 0 0 0 00 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 lsb
R udma_tenv udma_tsri
W
RESET:0 00000000 0 0 0 00 0 0