Freescale Semiconductor MPC5200B - Infrared SIR Divide Register (0 X4 C)-Irsdr; Infrared mir Divide Register (0 X50)-Irmdr; Infrared FIR Divide Register (0 X54)-Irfdr; Rx FIFO Number of Data (0 X58)-Rfnum

PSC Registers—MBAR + 0x2000, 0x2200, 0x2400, 0x2600, 0x2800, 0x2C00
MPC5200B Users Guide, Rev. 1
Freescale Semiconductor 15-5
PSC module operation is controlled by writing control bytes into the appropriate registers.
15.2.1 Mode Register 1 (0x00)—MR1
The Mode registers control configuration. MR1 can be read or written when the Mode register pointer points to it, at reset or after a reset Mode
register pointer command using CR[MISC]. After MR1 is read or written, the pointer points to MR2.
44 Infrared Control 1 (0x44)—IRCR1 8R/W
48 Infrared Control 2 (0x48)—IRCR2 8R/W
4C Infrared SIR Divide Register (0x4C)—IRSDR 8R/W
50 Infrared MIR Divide Register (0x50)—IRMDR 8R/W
54 Infrared FIR Divide Register (0x54)—IRFDR 8R/W
58 Rx FIFO Number of Data (0x58)—RFNUM 16 R
5C Tx FIFO Number of Data (0x5C)—TFNUM 16 R
60 Rx FIFO Data (0x60)—RFDATA 32 R/W
64 Rx FIFO Status (0x64)—RFSTAT 16 R/W
68 Rx FIFO Control (0x68)—RFCNTL 8R/W
6E Rx FIFO Alarm (0x6E)—RFALARM 16 R/W
72 Rx FIFO Read Pointer (0x72)—RFRPTR 16 R/W
76 Rx FIFO Write Pointer(0x76)—RFWPTR 16 R/W
7A Rx FIFO Last Read Frame (0x7A)—RFLRFPTR - Reserved 16 R/W
7C Rx FIFO Last Write Frame PTR (0x7C)—RFLWFPTR - Reserved 16 R/W
80 Tx FIFO Data (0x80)—TFDATA 32 R/W
84 Tx FIFO Status (0x84)—TFSTAT 16 R/W
88 Tx FIFO Control (0x88)—TFCNTL 8R/W
8E Tx FIFO Alarm (0x8E)—TFALARM 16 R/W
92 Tx FIFO Read Pointer (0x92)—TFRPTR 16 R/W
96 Tx FIFO Write Pointer (0x96)—TFWPTR 16 R/W
9A Tx FIFO Last Read Frame (0x9A)—TFLRFPTR - Reserved 16 R/W
9C Tx FIFO Last Write Frame PTR (0x9C)—TFLWFPTR - Reserved 16 R/W
Table 15-3. Mode Register 1 (0x00) for UART Mode
msb 01234567 lsb
R RxRTS RxIRQ/FFUL
L
Reserved PM PT B/C
W
RESET:00100000
Table 15-2. PSC Memory Map (continued)