List of Tables
Table Page
Number Number
MPC5200B Users Guide, Rev. 1
Freescale Semiconductor LOT-7
15-9 Stop-Bit Lengths ......................................................................................................................................................15-7
15-10 Status Register (0x04) for UART Mode .................................................................................................................15-8
15-11 Status Register (0x04) for SIR Mode ......................................................................................................................15-8
15-12 Status Register (0x04) for MIR / FIR Mode ...........................................................................................................15-8
15-13 Status Register (0x04) for other Modes ..................................................................................................................15-8
15-14 Clock Select Register (0x04) for UART / SIR Mode ...........................................................................................15-11
15-15 Clock Select Register (0x04) for other Modes ......................................................................................................15-11
15-16 Command Register (0x08) for all Modes ..............................................................................................................15-11
15-17 Rx Buffer Register (0x0C) for UART/SIR/MIR/FIR/Codec8/16/32 ..................................................................15-14
15-18 Rx Buffer Register (0x0C) for AC97 ...................................................................................................................15-14
15-19 Rx Buffer Register (0x0C) for Codec24 ..............................................................................................................15-14
15-20 Tx Buffer Register (0x0C) for UART/SIR/MIR/FIR/Codec8/16/32 Modes ........................................................15-15
15-21 TX Buffer Register (0x0C) for AC97) Modes ......................................................................................................15-15
15-22 Tx Buffer Register (0x0c) for Codec24 ................................................................................................................15-16
15-23 Input Port Change Register (0x10) for UART/SIR/MIR/FIR Modes ...................................................................15-16
15-24 PSC 1 Auxiliary Control Register (0x10) for all Modes ....................................................................
...................15-17
15-25 Interrupt Status Register (0x14) for UART / SIR Mode .......................................................................................15-18
15-26 Interrupt Status Register (0x14) other Modes .......................................................................................................15-18
15-27 Interrupt Mask Register (0x14) for UART / SIR Mode ........................................................................................15-19
15-28 Interrupt Mask Register (0x14) for other Modes ..................................................................................................15-19
15-29 Counter Timer Upper Register (0x18) for all Modes ............................................................................................15-20
15-30 Counter Timer Lower Register (0x1C) for all Modes ...........................................................................................15-20
15-31 Codec Clock Register (0x20)—CCR for Codec Mode .........................................................................................15-21
15-32 Codec Clock Register (0x20)—CCR for MIR/FIR Mode ....................................................................................15-21
15-33 Codec Clock Register (0x20)—CCR for other Modes .........................................................................................15-22
15-34 Interrupt Vector Register (0x30) for all Modes .....................................................................................................15-23
15-35 Input Port Register (0x34) for UART/SIR/MIR/FIR Modes ................................................................................15-23
15-36 Input Port Register (0x34) for Codec Mode ..........................................................................................................15-23
15-37 Input Port Register (0x34) for AC97 Mode ..........................................................................................................15-23
15-38 Output Port 1 Bit Set Register (0x38) for all Modes ......................................................................
.......................15-24
15-39 Output Port 0 Bit Set Register (0x3C) for all Modes ............................................................................................15-24
15-40 Serial Interface Control Register (0x40) for all Modes .........................................................................................15-25
15-41 Infrared Control 1 (0x44) for SIR Mode ...............................................................................................................15-28
15-42 Infrared Control 1 (0x44) for MIR/FIR Modes .....................................................................................................15-28
15-43 Infrared Control 2 (0x48) for MIR/FIR Modes .....................................................................................................15-28
15-44 Infrared Control 2 (0x48) for other Modes ...........................................................................................................15-28
15-45 Infrared SIR Divide Register (0x48) for SIR Mode ..............................................................................................15-29
15-46 Infrared SIR Divide Register (0x48) for other Modes ..........................................................................................15-29
15-47 Infrared MIR Divide Register (0x50) for MIR Mode ...........................................................................................15-30
15-48 Infrared MIR Divide Register (0x50) for other Modes .........................................................................................15-30
15-49 Frequency Selection in MIR Mode .......................................................................................................................15-31
15-50 Infrared FIR Divide Register (0x54) for MIR Mode .........................................................................
...................15-31
15-51 Infrared FIR Divide Register (0x54) for other Modes ..........................................................................................15-31
15-52 Frequency Selection for FIR Mode .......................................................................................................................15-32
15-53 RX FIFO Number of DATA (0x58) ......................................................................................................................15-33
15-54 Tx FIFO Number of Data (0x5C) ..........................................................................................................................15-33
15-55 Rx FIFO Status (0x64) ..........................................................................................................................................15-33
15-56 Rx FIFO Control (0x68) ........................................................................................................................................15-34
15-57 Rx FIFO Alarm (0x6E) .........................................................................................................................................15-34
15-58 Rx FIFO Read Pointer (0x72) ...............................................................................................................................15-35
15-59 Rx FIFO Write Pointer (0x76) ..............................................................................................................................15-35
15-60 Rx FIFO Last Read Frame (0x7A) ........................................................................................................................15-35
15-61 Rx FIFO Last Write Frame PTR (0x7C) ...............................................................................................................15-36
15-62 Tx FIFO STAT (0x84) ..........................................................................................................................................15-36
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