Freescale Semiconductor MPC5200B - Page 426

Host Control (HC) Operational Registers
MPC5200B Users Guide, Rev. 1
Freescale Semiconductor 12-23
Table 12-22. USB HC Rh Port1 Status Register
msb 012345678910 11 12131415
R
Reserved PRSC OCIC PSSC PESC CSC
W
RESET:0 000000000 0 0 0000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 lsb
R
Reserved LSDA PPS Reserved PRS POCI PSS PES CCS
W
RESET:0 00000 0 1000 0 0000
Bits Name Description
0:10 — Reserved
11 PRSC PortResetStatusChange—bit is set at the end of the 10ms port reset signal.
• Writing 1 causes HC to clear this bit.
• Writing 0 has no effect.
0 = Port reset not complete
1 = Port reset complete
12 OCIC PortOverCurrentIndicatorChange—bit is valid only if overcurrent conditions are reported on a
per-port basis. This bit is set when Root Hub changes the PortOverCurrentIndicator bit.
• Writing 1 causes HC to clear this bit.
• Writing 0 has no effect.
0 = No change in POCI
1 = POCI has changed
13 PSSC PortSuspendStatusChange—bit is set when the full resume sequence completes. Sequence
includes a 20s resume pulse, LS EOP, and 3ms resychronization delay.
• Writing 1 causes HC to clear this bit.
• Writing 0 has no effect.
This bit is also cleared when ResetStatusChange is set.
0 = Resume not complete
1 = Resume complete
14 PESC PortEnableStatusChange—bit is set when hardware events cause the PES bit to be cleared.
Changes from HCD writes do not set this bit.
• Writing 1 causes HC to clear this bit.
• Writing 0 has no effect.
0 = No change in PES
1 = Change in PES