Host Control (HC) Operational Registers
MPC5200B Users Guide, Rev. 1
Freescale Semiconductor 12-27
Bits Name Description
0:10 — Reserved
11 PRSC PortResetStatusChange—bit is set at the end of the 10ms port reset signal.
• Writing 1 clears this bit.
• Writing 0 has no effect.
0 = Port reset not complete
1 = Port reset complete
12 OCIC PortOverCurrentIndicatorChange—bit is valid only if overcurrent conditions are reported on a
per-port basis. This bit is set when Root Hub changes the PortOverCurrentIndicator bit.
• Writing 1 clears this bit.
• Writing 0 has no effect.
0 = No change in POCI
1 = POCI has changed
13 PSSC PortSuspendStatusChange—bit is set when the full resume sequence completes. Sequence
includes a 20s resume pulse, LS EOP, and 3ms resychronization delay.
• Writing 1 clears this bit.
• Writing 0 has no effect.
This bit is also cleared when ResetStatusChange is set.
0 = Resume not complete
1 = Resume complete
14 PESC PortEnableStatusChange—bit is set when hardware events cause the PES bit to be cleared.
• Writing 1clears this bit.
• Writing 0 has no effect.
0 = No change in PES
1 = Change in PES
15 CSC ConnectStatusChange—bit is set whenever a connect or disconnect event occurs.
• Writing 1 clears this bit.
• Writing 0 has no effect.
If CCS is cleared when a SetPortReset, SetPortEnable, or SetPortSuspend write occurs, this
bit is set to force the driver to re-evaluate the connection status since these writes should not
occur if the port is disconnected.
0 = No change in CCS
1 = Change in CCS
If the DeviceRemovable[NDP] bit is set, this bit is set only after a Root Hub reset to notify the
system that the device is attached.
16:21 — Reserved
22 LSDA LowSpeedDeviceAttached (read)—bit indicates the speed of the device attached to this port.
0 = Full speed device attached
1 = Low speed device attached
This field is valid only when CurrentConnectStatus is set.
ClearPortPower (write)
• Writing 1 causes HC to clear the PortPowerStatus bit.
• Writing 0 has no effect.
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