PSC Registers—MBAR + 0x2000, 0x2200, 0x2400, 0x2600, 0x2800, 0x2C00
MPC5200B Users Guide, Rev. 1
Freescale Semiconductor 15-9
Table 15-12. Status Register (0x04) for MIR / FIR Mode
msb 012345678 9 101112131415 lsb
REOF
PHYERR
Reserved
ORERR
URERR
TxRDY
FFULL
RxRDY
DEOF
Error Reserved
W
RESET:0 00000000 0 0 0 00 0 0
Table 15-13. Status Register (0x04) for other Modes
msb 012345678 9 101112131415 lsb
R
Reserved
ORERR
URERR
TxRDY
FFULL
RxRDY
Reserved
Error Reserved
CMD_SEND
DATA_OVR
DATA_VALID
UNEX_RX_
SLOT
W
RESET:0 00000000 0 0 0 00 0 0
Bit Name Description
0RB/
EOF
UART / SIR —Received Break—detects breaks originating in middle of received character. Such
a break must persist until the end of next detected character time.
0 = No break received.
1 = An all-0 character of the programmed length was received without a stop bit. RB is valid
only when RxRDY = 1. Only a single FIFO position is occupied when a break is received.
Further entries to FIFO are inhibited until RxD returns to high state for at least one-half
bit-time, which equals two successive PSC clock edges.
MIR / FIR—End of frame
0 = The next byte to be read from the RX-FIFO is not the last one of the frame.
1= The next byte to be read from the RX-FIFO is the last one of the frame. This bit is
effective when RxRDY=1.
other Modes—Reserved
1FE/
PHYERR
UART / SIR—Framing Error— is not used (always 0) in Codec mode.
0 = No framing error occurred.
1 = No stop bit detected when corresponding FIFO data character received. Stop bit-check
occurs in middle of first stop bit position. FE is valid only when RxRDY=1.
MIR / FIR—Physical layer error
0 = No error
1 = In MIR mode, this denotes that the RX received an abort. In FIR mode, this denotes that
there was a decode error. This bit can be cleared by the reset error status command in the
CR.
other Modes—Reserved
2PEUART / SIR—Parity Error—valid only if RxRDY = 1. PE is not used (always 0) in Codec mode.
0 = No parity error occurred.
1 = If MR1[PM]=0x (with parity or force parity), corresponding FIFO character was received
with incorrect parity. If MR1[PM]=11 (multidrop), PE stores received A/D bit.\
other Modes—Reserved
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