MPC5200B Users Guide, Rev. 1
15-40 Freescale Semiconductor
PSC Registers—MBAR + 0x2000, 0x2200, 0x2400, 0x2600, 0x2800, 0x2C00
15.2.34 Rx FIFO Read Pointer (0x72)—RFRPTR
15.2.35 Rx FIFO Write Pointer(0x76)—RFWPTR
15.2.36 Rx FIFO Last Read Frame (0x7A)—RFLRFPTR
Bit Name Description
0:3 — Reserved
4:15 ALARM “Almost full” threshold level. Amount of empty space remaining in the Rx FIFO at which the
ALARM bit in the status register goes high/active. See Section 15.4, PSC FIFO System for details.
Table 15-62. Rx FIFO Read Pointer (0x72)
msb 012345678 9 101112131415 lsb
R
Reserved R_PTR
W
RESET:0 00000000 0 0 0 00 0 0
Bit Name Description
0:3 — Reserved
4:15 R_PTR Read pointer.This FIFO-maintained pointer points to the next FIFO location to be read.
Table 15-63. Rx FIFO Write Pointer (0x76)
msb 012345678 9 101112131415 lsb
R
Reserved W_PTR
W
RESET:0 00000000 0 0 0 00 0 0
Bit Name Description
0:3 — Reserved
4:15 W_PTR Write pointer.This FIFO-maintained pointer points to the next FIFO location to be written to.
Table 15-64. Rx FIFO Last Read Frame (0x7A)
msb 012345678 9 101112131415 lsb
R Reserved LFP
W
RESET
:
0 00000000 0 0 0 00 0 0
Bit Name Description
0:3 — Reserved
4:15 LFP Last Frame Pointer. Not applicable to PSC FIFOs, since the PSCs do not recognize frame
formats in the serial data stream.
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