Freescale Semiconductor MPC5200B - Page 601

Freescale Semiconductor MPC5200B

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XLB Arbiter

Notes

MPC5200B Users Guide, Rev. 1

16-14 Freescale Semiconductor

Table of Contents

Default Chapter1
- Mpc5200B Users Guide1
- Table of Contents2
- MPC5200B Users Guide23
- List of Tables24
- External Signals27
Chapter 1 Introduction36
- Overview36
- Features36
- Architecture37
- Simplified Block Diagram—Mpc520038
- Block Diagram38
- Embedded G2_LE Core40
- Bestcomm I/O Subsystem41
- Programmable Serial Controllers (Pscs)41
- 10/100 Ethernet Controller41
- Universal Serial Bus (USB)41
- Infrared Support41
- Inter-Integrated Circuit (I 2 C)41
- Serial Peripheral Interface (SPI)41
- Byte Data Link Controller - Digital BDLC-D42
- System Level Interfaces42
- Chip Selects42
- Interrupt Controller42
- Timers42
- General Purpose Input/Outputs (GPIO)42
- Functional Pin Multiplexing43
- Real-Time Clock (RTC)43
- SDRAM Controller and Interface43
- Multi-Function External Localplus Bus43
- Power Management43
- Systems Debug and Test44
- Physical Characteristics44
Chapter 2 Signal Descriptions46
- Overview46
- Pin PBGA Pin Detail47
- Pin PBGA — Top View48
- Pinout Tables49
Chapter 3 Memory Map120
- Overview120
- Internal Register Memory Map121
- MPC5200 Memory Map122
- MPC5200 Internal Register Space122
- External Busses122
- SDRAM Bus122
- Localplus Bus123
- Memory Map Space Register Description124
- Memory Address Base Register -MBAR + 0X0000124
- Boot and Chip Select Addresses124
- SDRAM Chip Select Configuration Registers125
- IPBI Control Register and Wait State Enable -Mbar+0X0054127
Chapter 4 Resets and Reset Configuration128
- Overview128
- Hard and Soft Reset Pins128
- Power-On Reset-PORESET128
  - Hard Reset—Hreset128
  - Soft Reset—Sreset129
- Reset Operation129
- Reset Sequence129
- Other Resets130
- Internal Hard Reset Vs External HRESET Assertion130
  - Reset Configuration131
Chapter 5 Clocks and Power Management134
- Clock Distribution Module (CDM)134
- Overview134
- Primary Synchronous Clock Domains135
- MPC5200 Clock Relations136
Chapter 6 G2_LE Processor Core159
- Not Supported Instruction159
- Not Supported XLB Parity Feature159
Chapter 7 System Integration Unit (SIU)163
- Interface Description163
  - Programming Note163
  - Interrupt Controller Registers164
- GPIO Pin Multiplexing184
- Gpio/Generic MUX Cell184
- GPIO Programmer's Model187
- Slice Timers221
Chapter 8 SDRAM Memory Controller234
- Terminology and Notation234
- Endian"-Ness234
- Block Diagram249
- Operation252
  - Power-Up Initialization252
  - Read Clock253
- Programming the SDRAM Controller253
- Memory Controller Registers (Mbar+0X0100:0X010C)255
- Address Bus Mapping263
Chapter 9 Localplus Bus (External Bus Interface)267
- Interface267
- External Signals267
- LPC Concept Diagram268
  - Non-Muxed Mode269
- Muxed Mode Address Latching269
- Output Enable Signal269
- Timing Diagram - Muxed Mode274
  - Chip Selects Configuration275
  - Reset Configuration275
- DMA (Bestcomm) Interface (SCLPC)276
- Programmer's Model276
- PCI External Signals299
Chapter 10 PCI Controller300
- PCI_AD[31:0] - Address/Data Bus300
- PCI_DEVSEL - Device Select300
- PCI_FRAME - Frame300
- PCI_IDSEL - Initialization Device Select300
- PCI_IRDY - Initiator Ready300
- Pci Controller Type 0 Configuration Space303
- Registers304
  - Global Status/Control Register Pcigscr(Rw) —Mbar + 0X0D310
  - Configuration Address Register Pcicar (Rw) —Mbar + 0X0Df320
  - Tx Enables Pciter(Rw)—Mbar + 0X380C323
  - Tx Next Address Pcitnar(R) —Mbar + 0X324
  - Tx Packets Done Counts Pcitpdcr(R) —Mbar + 0X325
  - Tx Status Pcitsr(Rwc) —Mbar + 0X381C326
  - Tx Fifo Data Register Pcitfdr(Rw) —Mbar + 0X327
  - Tx FIFO Status Register PCITFSR(R/RWC) —MBAR + 0X3844328
  - Tx FIFO Alarm Register PCITFAR(RW) —MBAR + 0X384C329
  - Tx FIFO Control Register PCITFCR(RW) —MBAR + 0X3848329
  - Multi-Channel DMA Receive Interface331
- PCI Bus Protocol342
  - PCI Bus Background342
  - Basic Transfer Control342
  - PCI Transactions343
- PCI Read Terminated by Master343
  - PCI Bus Commands344
- PCI Write Terminated by Target344
  - Addressing345
  - Memory Space Addressing345
  - Configuration Space Addressing and Transactions346
  - I/O Space Addressing346
  - Address Decoding347
- Contents of the AD Bus During Address Phase of a Type 0 Configuration Transaction347
- Contents of the AD Bus During Address Phase of a Type 1 Configuration Transaction347
- Initiator Arbitration348
  - Priority Scheme348
  - Configuration Interface348
- XL Bus Initiator Interface348
- Initiator Arbitration Block Diagram348
  - Endian Translation349
  - Configuration Mechanism351
- Type 0 Configuration Translation351
  - Type 0 Configuration Translation352
  - Interrupt Acknowledge Transactions353
  - Special Cycle Transactions353
  - Type 1 Configuration Translation353
  - Transaction Termination354
- XL Bus Target Interface354
  - Reads from Local Memory355
  - Local Memory Writes355
    - Data Translation355
  - Target Abort356
  - Latrule Disable356
- Communication Sub-System Initiator Interface356
  - Access Width357
  - PCI - Supported Clock Ratios359
  - Interrupts359
    - PCI Bus Interrupts359
    - Internal Interrupt359
- PCI Arbiter359
- Application Information360
  - XL Bus Initiated Transaction Mapping360
  - Address Maps361
    - Address Translation361
      - Inbound Address Translation361
      - Outbound Address Translation362
- Inbound Address Map362
  - Base Address Register Overview363
- Outbound Address Map363
  - XL Bus Arbitration Priority364
- Bestcomm Key Features366
- Overview366
Chapter 11 ATA Controller366
- Bestcomm Read366
- ATA Controller Interface366
  - Bestcomm Write367
- ATA Register Interface367
- ATA Host Controller Operation385
  - PIO State Machine386
  - DMA State Machine387
    - Software Requirements387
- Signals and Connections388
- ATA Interface Description389
- Connections—Controller Cable, System Board, MPC5200389
- ATA Bus Background391
- ATA Sector Format394
  - ATA Transactions395
- ATA Reset/Power-Up401
  - Hardware Reset401
  - Software Reset401
- ATA I/O Cable Specifications402
- Timing Diagram—Reset Timing402
Chapter 12 Universal Serial Bus (USB)404
- Data Transfer Types404
- Overview404
- USB Focus Areas404
- Host Controller Interface405
- Communication Channels405
  - Data Structures406
- Typical List Structure406
- Interrupt ED Structure407
- Host Control (HC) Operational Registers408
  - Programming Note408
- Sample Interrupt Endpoint Schedule408
Chapter 13 Bestcomm435
- Features Summary435
- Descriptors436
- Tasks436
- Task Descriptor Table461
- Variable Table461
- Context Save Area461
- On-Chip SRAM461
- Programming Model461
- Task Table461
Chapter 14 Fast Ethernet Controller (FEC)468
- Full- and Half-Duplex Operation468
- Mbps and 100Mbps MII Interface Operation468
- Mbps 7-Wire Interface Operation468
- Address Recognition Options468
- Internal Loopback468
- I/O Signal Overview468
  - Detailed Signal Descriptions469
    - MII Ethernet MAC-PHY Interface469
    - MII Management Frame Structure470
      - MII Management Register Set471
- FEC Memory Map and Registers471
  - Top Level Module Memory Map471
  - Control and Status (CSR) Memory Map472
  - MIB Block Counters Memory Map473
  - FIFO Interface492
- Hardware Controlled Initialization499
- User Initialization (Prior to Asserting ETHER_EN)500
  - Microcontroller Initialization500
- Frame Control/Status Words500
  - Receive Frame Status Word500
  - Transmit Frame Control Word501
- Network Interface Options502
- FEC Frame Reception502
- Ethernet Address Recognition503
- Ethernet Address Recognition - Receive Block Decisions504
- Ethernet Address Recognition - Microcode Decisions505
- Full-Duplex Flow Control507
- Inter-Packet Gap Time508
- Collision Handling508
- Internal and External Loopback509
- Ethernet Error-Handling Procedure509
  - Transmission Errors509
  - Reception Errors509
- Psc Functions Overview513
  - Status Register (0X04) — SR515
  - Clock Select Register (0X04) — CSR515
  - Command Register (0X08)—Cr515
  - Rx Buffer Register (0X0C) — RB515
  - Tx Buffer Register (0X0C)—Tb515
  - Infrared SIR Divide Register (0X4C)—Irsdr516
  - Infrared mir Divide Register (0X50)—Irmdr516
  - Infrared FIR Divide Register (0X54)—Irfdr516
  - Rx FIFO Number of Data (0X58)—Rfnum516
  - Tx FIFO Number of Data (0X5C)—Tfnum516
- PSC Operation Modes542
  - PSC in UART Mode555
  - PSC in Codec Mode560
    - Block Diagram and Signal Definition for Codec Mode561
  - PSC in AC97 Mode572
    - Block Diagram and Signal Definition for AC97 Mode573
    - AC97 Low-Power Mode574
- PSC in SIR Mode576
  - Block Diagram and Signal Definition for SIR Mode576
  - Transmitting and Receiving in SIR Mode577
  - Configuration Sequence Example for SIR Mode578
- PSC in mir Mode578
  - Block Diagram and Signal Definition for mir Mode578
  - Transmitting and Receiving in mir Mode579
- Serial Interaction Pulse (SIP)580
  - Configuration Sequence Example for mir Mode580
- PSC in FIR Mode581
  - Block Diagram and Signal Definition for FIR Mode581
  - Transmitting and Receiving in FIR Mode581
  - Configuration Sequence Example for FIR Mode582
- PSC FIFO System582
  - Rx Fifo582
  - Tx Fifo582
- Looping Modes585
  - Automatic Echo Mode585
  - Local Loop-Back Mode585
  - Remote Loop-Back Mode586
- Multidrop Mode586
- Purpose588
Chapter 20 Byte Data Link Controller (BDLC)468
- Modes of Operation468
Chapter 16 XLB Arbiter588
- Prioritization588
- Block Diagram of XLB Arbiter588
Chapter 21 Debug Support and JTAG Interface588
- Overview588
Chapter 19 Motorola Scalable CAN (MSCAN)602
- Features602
- SPI Signal Description603
- Modes of Operation603
Chapter 17 Serial Peripheral Interface (SPI )603
- Master In/Slave out (MISO)603
- Master Out/Slave in (MOSI)603
- Serial Clock (SCK)603
- Slave Mode610
Chapter 18 Inter-Integrated Circuit (IC)618
- Features618
- START Signal619
- STOP Signal619
  - Slave Address Transmission620
  - Data Transfer620
  - Acknowledge620
  - Repeated Start621
  - Clock Synchronization and Arbitration621
  - Timing Diagram—Receiver Acknowledgement621
- Data Transfer, Combined Format621
  - Timing Diagram—Clock Synchronization622
  - Timing Diagram—Arbitration Procedure622
  - System Clock624
- Transfer Initiation and Interrupt636
  - RXCAN — CAN Receiver Input Pin641
  - TXCAN — CAN Transmitter Output Pin641
- CAN System642
- Memory Map / Register Definition643
  - Module Memory Map643
  - Register Descriptions643
  - MSCAN Control Register 1 (CANCTL1)—MBAR + 0X0901646
  - MSCAN Bus Timing Register 1 (CANBTR1)—MBAR + 0X0905648
  - MSCAN Receiver Interrupt Enable Register (CANRIER)—MBAR + 0X0909651
  - MSCAN Transmitter Flag Register (CANTFLG)—MBAR + 0X090C652
  - MSCAN Transmitter Interrupt Enable Register (Cantier)—Mbar+0X090D653
  - MSCAN Transmitter Message Abort Request(CANTARQ)—MBAR + 0X0910653
  - MSCAN Transmitter Message Abort Ack(CANTAAK)—MBAR +0X0911654
  - MSCAN Transmit Buffer Selection (CANTBSEL)—MBAR + 0X0914654
  - MSCAN ID Acceptance Control Register (CANIDAC)—MBAR + 0X0915655
  - MSCAN Receive Error Counter Register (CANRXERR)—MBAR + 0X091C656
  - MSCAN Transmit Error Counter Register (CANTXERR)—MBAR + 0X091D656
  - MSCAN ID Mask Register (CANIDMR0-7)—MBAR + 0X0928659
- Programmer's Model of Message Storage661
  - Data Segment Registers (Dsr)663
  - Identifier Registers (Idr)663
  - Data Length Register (DLR)664
  - Message Storage666
    - Message Transmit Background666
- User Model for Message Buffer Organization666
  - Transmit Structures667
  - Receive Structures667
  - Identifier Acceptance Filter668
- Bit Maskable Identifier Acceptance Filter669
- Bit Maskable Identifier Acceptance Filters669
  - Protocol Violation Protection670
- Bit Maskable Identifier Acceptance Filters670
  - Clock System671
- MSCAN Clocking Scheme671
- Segments Within the Bit Time672
  - Timer Link673
  - Low Power Options673
- Sleep Request / Acknowledge Cycle674
  - MSCAN Initialization Mode675
- Simplified State Transitions for Entering/Leaving Sleep Mode675
  - MSCAN Power down Mode676
  - Programmable Wake-Up Function676
  - Description of Interrupt Operation676
- Initialization Request/Acknowledge Cycle676
  - Transmit Interrupt677
  - Receive Interrupt677
  - Wake-Up Interrupt677
  - Error Interrupt678
  - Interrupt Acknowledge678
  - Recovery from STOP or WAIT678
- BDLC Operating Modes State Diagram681
- BDLC Block Diagram683
- Signal Description684
  - BDLC Control Register 1 (DLCBCR1)—MBAR + 0X1300684
  - Detailed Signal Descriptions684
  - Memory Map and Registers684
  - Module Memory Map684
  - Overview684
  - Register Descriptions684
  - RXB - BDLC Receive Pin684
  - TXB - BDLC Transmit Pin684
  - BDLC State Vector Register (DLCBSVR) - MBAR + 0X1300686
  - BDLC Control Register 2 (DLCBCR2) - MBAR + 0X1304687
- Types of In-Frame Response689
  - BDLC Data Register (DLCBDR) - MBAR + 0X1305691
  - BDLC Analog Round Trip Delay Register (DLCBARD) - MBAR + 0X1308691
  - BDLC Rate Select Register (DLCBRSR) - MBAR + 0X1309693
  - BDLC Control Register (DLCSCR) - MBAR + 0X130C694
  - BDLC Status Register (DLCBSTAT) - MBAR + 0X130D694
  - General695
- Functional Description695
  - J1850 Frame Format695
- J1850 Bus Message Format (VPW)695
- J1850 VPW Symbols696
  - J1850 VPW Symbols697
  - J1850 VPW Valid/Invalid Bits & Symbols698
- J1850 VPW Passive Symbols701
- J1850 VPW EOF and IFS Symbols702
- J1850 VPW Active Symbols703
- J1850 VPW BREAK Symbol703
- J1850 VPW Bitwise Arbitrations704
  - J1850 Bus Errors705
  - Mux Interface706
    - Mux Interface - Rx Digital Filter706
  - Protocol Handler707
- BDLC Module Rx Digital Filter Block Diagram707
  - Protocol Architecture708
- BDLC Protocol Handler Outline708
  - Transmitting a Message709
  - Receiving a Message712
- Basic BDLC Transmit Flowchart712
  - BDLC Reception Control Bits713
  - Receiving a Message with the BDLC Module713
  - Filtering Received Messages713
  - Receiving Exceptions713
  - Transmitting an In-Frame Response (IFR)715
- Basic BDLC Receive Flowchart715
  - IFR Types Supported by the BDLC Module716
  - BDLC IFR Transmit Control Bits716
  - Transmit Single Byte IFR717
  - Transmit Multi-Byte IFR 1717
  - Transmit Multi-Byte IFR 0717
  - Transmitting an IFR with the BDLC Module717
- Transmitting a Type 1 IFR719
- Transmitting a Type 2 IFR720
  - Transmitting IFR Exceptions721
  - Receiving an In-Frame Response (IFR)722
- Transmitting a Type 3 IFR722
  - Receiving an IFR with the BDLC Module723
  - Receiving IFR Exceptions724
  - Special BDLC Module Operations724
    - Transmitting or Receiving a Block Mode Message724
- Receiving an IFR with the BDLC Module724
  - Transmitting or Receiving a Message in 4X Mode725
  - BDLC Module Initialization726
  - Initialization Sequence726
- Basic BDLC Module Transmit Flowchart726
  - Initializing the Configuration Bits727
  - Exiting Loopback Mode and Enabling the BDLC Module727
  - Enabling BDLC Interrupts727
- Resets729
- General729
- Basic BDLC Module Initialization Flowchart729
- TAP Link Module (TLM) and Slave TAP Implementation730
- Overview730
- Generic TLM/TAP Architecture Diagram731
- Generic TAP Link Module (TLM) Diagram732
- TLM and TAP Signal Descriptions733
  - Test Reset (TRST)733
  - Test Clock (TCK)733
  - Test Mode Select (TMS)733
  - Test Data in (TDI)733
- Generic Slave TAP733
  - Test Data out (TDO)734
- Slave Test Reset (STRST)734
  - Enable Slave—Ena[0:N]734
  - Select DR Link—Sel[0:N]734
  - Slave Test Data Out—Stdo[0:N]734
- TAP State Machines734
- State Diagram—Tap Controller735
- TLM Link DR Instructions736
  - Tlm:tlmena737
  - Tlm:ppcena737
- TLM Test Instructions737
  - Idcode737
    - Device ID Register737
  - Bypass737
  - Sample/Preload737
  - Extest738
  - Clamp738
  - Highz738
  - Interrupt and Bus Errors753
  - PCI Controller Type 0 Configuration Space754
  - Communication Sub-System Interface Registers754
  - I 2 C Status Register (MSR)—MBAR + 0X3D0C759