Table Of Contents
Paragraph Page
Number Number
MPC5200B Users Guide, Rev. 1
TOC-6 Freescale Semiconductor
9.7.4.4 LPC Rx/Tx FIFO Alarm Register—MBAR + 0x3C4C ............................................................................9-30
9.7.4.5 LPC Rx/Tx FIFO Read Pointer Register—MBAR + 0x3C50 ..................................................................9-30
9.7.4.6 LPC Rx/Tx FIFO Write Pointer Register—MBAR + 0x3C54 ..................................................................9-31
Chapter 10 PCI Controller
10.1 Overview .................................................................................................................................................................10-1
10.1.1 Features .............................................................................................................................................................10-1
10.1.2 Block Diagram ..................................................................................................................................................10-2
10.2 PCI External Signals ...............................................................................................................................................10-2
10.2.1 PCI_AD[31:0] - Address/Data Bus ..................................................................................................................10-3
10.2.2 PCI_CXBE[3:0] - Command/Byte Enables ......................................................................................................10-3
10.2.3 PCI_DEVSEL - Device Select ..........................................................................................................................10-3
10.2.4 PCI_FRAME - Frame .......................................................................................................................................10-3
10.2.5 PCI_IDSEL - Initialization Device Select ........................................................................................................10-3
10.2.6 PCI_IRDY - Initiator Ready .............................................................................................................................10-3
10.2.6.1 PCI_PAR - Parity .......................................................................................................................................10-3
10.2.7 PCI_CLK - PCI Clock ......................................................................................................................................10-3
10.2.8 PCI_PERR - Parity Error ..................................................................................................................................10-3
10.2.9 PCI_RST - Reset ...............................................................................................................................................10-3
10.2.10 PCI_SERR - System Error ................................................................................................................................10-3
10.2.11 PCI_STOP - Stop ..............................................................................................................................................10-3
10.2.12 PCI_TRDY - Target Ready ..............................................................................................................................10-3
10.3 Registers ..................................................................................................................................................................10-4
10.3.1 PCI Controller Type 0 Configuration Space .....................................................................................................10-6
10.3.1.1 Device ID/ Vendor ID Registers PCIIDR(R) —MBAR + 0x0D00 ...........................................................10-7
10.3.1.2 Status/Command Registers PCISCR(R/RW/RWC) —MBAR + 0x0D04 .................................................10-8
10.3.1.3 Revision ID/ Class Code Registers PCICCRIR(R) —MBAR + 0x0D08 ................................................10-10
10.3.1.4 Configuration 1 Register PCICR1(R/RW) —MBAR + 0x0D0C ............................................................10-10
10.3.1.5 Base Address Register 0 PCIBAR0(RW) —MBAR + 0x0D10 ..............................................................10-11
10.3.1.6 Base Address Register 1 PCIBAR1(RW) —MBAR + 0x0D14 ..............................................................10-12
10.3.1.7 CardBus CIS Pointer Register PCICCPR(RW) —MBAR + 0x0D28 ......................................................10-12
10.3.1.8 Subsystem ID/ Subsystem Vendor ID Registers PCISID(R)—MBAR + 0x0D2C .................................10-12
10.3.1.9 Expansion ROM Base Address PCIERBAR(R) —MBAR + 0x0D30 ....................................................10-12
10.3.1.10 Capabilities Pointer (Cap_Ptr) PCICPR(R)—MBAR + 0x0D34 .............................................................10-12
10.3.1.11 Configuration 2 Register PCICR2 (R/RW) —MBAR + 0x0D3C ...........................................................10-13
10.3.2 General Control/Status Registers ....................................................................................................................10-13
10.3.2.1 Global Status/Control Register PCIGSCR(RW) —MBAR + 0x0D60 ....................................................10-13
10.3.2.2 Target Base Address Translation Register 0 PCITBATR0(RW) —MBAR + 0x0D64 ...........................10-15
10.3.2.3 Target Base Address Translation Register 1 PCITBATR1(RW) —MBAR + 0x0D68 ...........................10-15
10.3.2.4 Target Control Register PCITCR(RW) —MBAR + 0x0D6C .................................................................10-16
10.3.2.5 Initiator Window 0 Base/Translation Address Register PCIIW0BTAR(RW)—MBAR + 0x0D70 ........10-16
10.3.2.6 Initiator Window 1 Base/Translation Address Register PCIIW1BTAR(RW) —MBAR + 0x0D74 .......10-17
10.3.2.7 Initiator Window 2 Base/Translation Address Register PCIIW2BTAR(RW) —MBAR + 0x0D78 .......10-18
10.3.2.8 Initiator Window Configuration Register PCIIWCR(RW) —MBAR + 0x0D80 ....................................10-18
10.3.2.9 Initiator Control Register PCIICR(RW) —MBAR + 0x0D84 .................................................................10-19
10.3.2.10 Initiator Status Register PCIISR(RWC) —MBAR + 0x0D88 .................................................................10-20
10.3.2.11 PCI Arbiter Register PCIARB(RW) —MBAR + 0x0D8C ......................................................................10-20
10.3.2.12 Configuration Address Register PCICAR (RW) —MBAR + 0x0DF8 ....................................................10-21
10.3.3 Communication Sub-System Interface Registers ...........................................................................................10-21
10.3.3.1 Multi-Channel DMA Transmit Interface ..................................................................................................10-21
10.3.3.1.1 Tx Packet Size PCITPSR(RW) —MBAR + 0x3800 .........................................................................10-22
10.3.3.1.2 Tx Start Address PCITSAR(RW) —MBAR + 0x3804 .....................................................................10-22
10.3.3.1.3 Tx Transaction Control Register PCITTCR(RW) —MBAR + 0x3808 ............................................10-22
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