MPC5200B Users Guide, Rev. 1
Freescale Semiconductor B-1
Appendix B
List of Registers
Section 5.5 CDM Registers ............................................................................................................................................5-11
5.5.1 CDM JTAG ID Number Register—MBAR + 0x0200 ......................................................................... 5-12
5.5.2 CDM Power On Reset Configuration Register—MBAR + 0x0204 .................................................... 5-12
5.5.3 CDM Bread Crumb Register—MBAR + 0x0208 ................................................................................ 5-14
5.5.4 CDM Configuration Register—MBAR + 0x020C............................................................................... 5-14
5.5.5 CDM 48MHz Fractional Divider Configuration Register—MBAR + 0x0210.................................... 5-15
5.5.6 CDM Clock Enable Register—MBAR + 0x0214 ................................................................................ 5-16
5.5.7 CDM System Oscillator Configuration Register—MBAR + 0x0218.................................................. 5-17
5.5.8 CDM Clock Control Sequencer Configuration Register—MBAR + 0x021C ..................................... 5-18
5.5.9 CDM Soft Reset Register—MBAR + 0x0220 ..................................................................................... 5-20
5.5.10 CDM System PLL Status Register—MBAR + 0x0224 ....................................................................... 5-20
5.5.11 PSC1 Mclock Config Register—MBAR + 0x0228 ............................................................................. 5-21
5.5.12 PSC2 Mclock Config Register—MBAR + 0x022C............................................................................. 5-22
5.5.13 PSC3 Mclock Config Register—MBAR + 0x0230 ............................................................................. 5-22
5.5.14 PSC6 (IrDA) Mclock Config Register—MBAR + 0x0234 ................................................................. 5-23
Section 7.2.4 Interrupt Controller Registers....................................................................................................................... 8-5
7.2.4.1 ICTL Peripheral Interrupt Mask Register—MBAR + 0x0500............................................................... 8-5
7.2.4.2 ICTL Peripheral Priority and HI/LO Select 1 Register —MBAR + 0x0504......................................... 8-7
7.2.4.3 ICTL Peripheral Priority and HI/LO Select 2 Register —MBAR + 0x0508......................................... 8-8
7.2.4.4 ICTL Peripheral Priority and HI/LO Select 3 Register —MBAR + 0x050C........................................ 8-8
7.2.4.5 ICTL External Enable and External Types Register —MBAR + 0x0510.............................................. 8-9
7.2.4.6 ICTL Critical Priority and Main Interrupt Mask Register—MBAR + 0x0514.................................... 8-10
7.2.4.7 ICTL Main Interrupt Priority and INT/SMI Select 1 Register —MBAR + 0x0518 ........................... 8-12
7.2.4.8 ICTL Main Interrupt Priority and INT/SMI Select 2 Register—MBAR + 0x051C............................ 8-13
7.2.4.9 ICTL Perstat, MainStat, MainStat, CritStat Encoded Register—MBAR + 0x0524............................. 8-14
7.2.4.10 ICTL Critical Interrupt Status All Register—MBAR + 0x0528 .......................................................... 8-15
7.2.4.11 ICTL Main Interrupt Status All Register—MBAR + 0x052C ............................................................. 8-16
7.2.4.12 ICTL Peripheral Interrupt Status All Register—MBAR + 0x0530...................................................... 8-17
7.2.4.13 ICTL Peripheral Interrupt Status All Register—MBAR + 0x0538...................................................... 8-18
7.2.4.14 ICTL Main Interrupt Emulation All Register—MBAR + 0x0540....................................................... 8-19
7.2.4.15 ICTL Peripheral Interrupt Emulation All Register—MBAR + 0x0544............................................... 8-20
7.2.4.16 ICTL IRQ Interrupt Emulation All Register—MBAR + 0x0548 ........................................................ 8-21
Section
7.3.2.1 GPIO Standard Registers—MBAR+0x0B00 ............................................................................................ 8-28
7.3.2.1.1 GPS Port Configuration Register—MBAR + 0x0B00......................................................................... 8-29
7.3.2.1.2 GPS Simple GPIO Enables Register—MBAR + 0x0B04.................................................................... 8-31
7.3.2.1.3 GPS Simple GPIO Open Drain Type Register —MBAR + 0x0B08.................................................... 8-33
7.3.2.1.4 GPS Simple GPIO Data Direction Register—MBAR + 0x0B0C ........................................................ 8-34
7.3.2.1.5 GPS Simple GPIO Data Output Values Register —MBAR + 0x0B10 ................................................ 8-37
7.3.2.1.6 GPS Simple GPIO Data Input Values Register —MBAR + 0x0B14................................................... 8-38
7.3.2.1.7 GPS GPIO Output-Only Enables Register —MBAR + 0x0B18 ......................................................... 8-39
7.3.2.1.8 GPS GPIO Output-Only Data Value Out Register —MBAR + 0x0B1C............................................. 8-40
7.3.2.1.9 GPS GPIO Simple Interrupt Enable Register—MBAR + 0x0B20 ...................................................... 8-41
7.3.2.1.10 GPS GPIO Simple Interrupt Open-Drain Emulation Register —MBAR + 0x0B24............................ 8-42
7.3.2.1.11 GPS GPIO Simple Interrupt Data Direction Register —MBAR + 0x0B28......................................... 8-43
7.3.2.1.12 GPS GPIO Simple Interrupt Data Value Out Register —MBAR + 0x0B2C....................................... 8-43
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