MPC5200B Users Guide, Rev. 1
Freescale Semiconductor B-7
Section 14.8 FEC Tx FIFO Status Register—MBAR + 0x31A8.................................................................................. 14-28
14.8.1 FEC Rx FIFO Control Register—MBAR + 0x318C ......................................................................... 14-29
14.8.2 FEC Rx FIFO Last Read Frame Pointer Register—MBAR + 0x3190 .............................................. 14-30
14.8.3 FEC Rx FIFO Last Write Frame Pointer Register—MBAR + 0x3194.............................................. 14-31
14.8.4 FEC Rx FIFO Alarm Pointer Register—MBAR + 0x3198 ............................................................... 14-31
14.8.5 FEC Rx FIFO Read Pointer Register—MBAR + 0x319C................................................................. 14-32
14.8.6 FEC Rx FIFO Write Pointer Register—MBAR + 0x31A0................................................................ 14-33
14.8.7 FEC Reset Control Register—MBAR + 0x31C4............................................................................... 14-33
14.8.8 FEC Transmit FSM Register—MBAR + 0x31C8.............................................................................. 14-34
Section 15.2 PSC Registers—MBAR + 0x2000, 0x2200, 0x2400, 0x2600, 0x2800, 0x2C00 ...................................... 15-4
15.2.1 Mode Register 1 (0x00)—MR1............................................................................................................ 15-5
15.2.2 Mode Register 2 (0x00) — MR2.......................................................................................................... 15-7
15.2.3 Status Register (0x04) — SR................................................................................................................ 15-8
15.2.4 Clock Select Register (0x04) — CSR ................................................................................................ 15-12
15.2.5 Command Register (0x08)—CR ........................................................................................................ 15-12
15.2.6 Rx Buffer Register (0x0C) — RB ...................................................................................................... 15-15
15.2.7 Tx Buffer Register (0x0C)—TB......................................................................................................... 15-16
15.2.8 Input Port Change Register (0x10) — IPCR ...................................................................................... 15-17
15.2.9 Auxiliary Control Register (0x10) — ACR........................................................................................ 15-18
15.2.10 Interrupt Status Register (0x14) — ISR ............................................................................................. 15-19
15.2.11 Interrupt Mask Register (0x14)—IMR............................................................................................... 15-20
15.2.12 Counter Timer Upper Register (0x18)—CTUR ................................................................................. 15-22
15.2.13 Counter Timer Lower Register (0x1C)—CTLR ................................................................................ 15-23
15.2.14 Codec Clock Register (0x20)—CCR.................................................................................................. 15-23
15.2.18 Interrupt Vector Register (0x30)—IVR .............................................................................................. 15-27
15.2.19 Input Port Register (0x34)—IP........................................................................................................... 15-28
15.2.20 Output Port 1 Bit Set (0x38)—OP1.................................................................................................... 15-29
15.2.21 Output Port 0 Bit Set (0x3C)—OP0 ................................................................................................... 15-29
15.2.22 Serial Interface Control Register (0x40)—SICR................................................................................ 15-30
15.2.23 Infrared Control 1 (0x44)—IRCR1 .................................................................................................... 15-33
15.2.24 Infrared Control 2 (0x48)—IRCR2 .........................................................................................
........... 15-33
15.2.25 Infrared SIR Divide Register (0x4C)—IRSDR.................................................................................. 15-34
15.2.26 Infrared MIR Divide Register (0x50)—IRMDR ................................................................................ 15-35
15.2.27 Infrared FIR Divide Register (0x54)—IRFDR................................................................................... 15-36
15.2.28 Rx FIFO Number of Data (0x58)—RFNUM ..................................................................................... 15-38
15.2.29 Tx FIFO Number of Data (0x5C)—TFNUM..................................................................................... 15-38
15.2.30 Rx FIFO Data (0x60)—RFDATA....................................................................................................... 15-38
15.2.31 Rx FIFO Status (0x64)—RFSTAT ..................................................................................................... 15-38
15.2.32 Rx FIFO Control (0x68)—RFCNTL.................................................................................................. 15-39
15.2.33 Rx FIFO Alarm (0x6E)—RFALARM................................................................................................ 15-39
15.2.34 Rx FIFO Read Pointer (0x72)—RFRPTR.......................................................................................... 15-40
15.2.35 Rx FIFO Write Pointer(0x76)—RFWPTR ......................................................................................... 15-40
15.2.36 Rx FIFO Last Read Frame (0x7A)—RFLRFPTR.............................................................................. 15-40
15.2.37 Rx FIFO Last Write Frame PTR (0x7C)—RFLWFPTR .................................................................... 15-41
15.2.38 Tx FIFO Data (0x80)—TFDATA....................................................................................................... 15-41
15.2.39 Tx FIFO Status (0x84)—TFSTAT...................................................................................................... 15-41
15.2.40 Tx FIFO Control (0x88)—TFCNTL .................................................................................................. 15-42
15.2.41 Tx FIFO Alarm (0x8E)—TFALARM ................................................................................................ 15-42
15.2.42 Tx FIFO Read Pointer (0x92)—TFRPTR .......................................................................................... 15-42
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