Lenze 8400 StateLine C - L_Dflipflop_1

Firmware ≤ 11.00 - DMS 8.0 EN - 10/2011 L 793
8400 StateLine C | Reference manual
Function library
Function blocks | L_DFlipFlop_1
16.1.14 L_DFlipFlop_1
The FB saves binary signals (DFlipFlop) in a clock-controlled way.
Inputs
Outputs
Function
If the bClr input = FALSE, a signal edge at the bClk input switches the static input signal bD
to the bOut output, where it is retained:
Identifier
Data type
Information/possible settings
bD
BOOL
Data input
bClk
BOOL
Clock input
• Only FALSE/TRUE edges are evaluated
bClr
BOOL
Reset input
TRUE • The bOut output is set to FALSE.
•The bNegOut output is set to TRUE.
Identifier
Data type
Value/meaning
bOut
BOOL
Output signal
bNegOut
BOOL
Output signal, inverted
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E&ON
E&OU
E'
&/5
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E2XW
E1HJ2XW
4
4
TRUE
TRUE
FALSE
FALSE
bClk
bOut
t
TRUE
FALSE
bD
t
t
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