Philips LPC2101 - Page 271

Philips Semiconductors
UM10161
Volume 1 Chapter 22: Supplementary information
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
User manual Rev. 01 — 12 January 2006 271
continued >>
Fig 31. Serial clock synchronization. . . . . . . . . . . . . . . .126
Fig 32. Format and states in the Master Transmitter
mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136
Fig 33. Format and states in the Master Receiver
mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137
Fig 34. Format and states in the Slave Receiver mode .138
Fig 35. Format and states in the Slave Transmitter
mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139
Fig 36. Simultaneous repeated START conditions from two
masters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147
Fig 37. Forced access to a busy I
2
C-bus . . . . . . . . . . .148
Fig 38. Recovering from a bus obstruction caused by a
LOW level on SDA . . . . . . . . . . . . . . . . . . . . . . .148
Fig 39. SPI data transfer format (CPHA = 0 and
CPHA = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158
Fig 40. SPI block diagram . . . . . . . . . . . . . . . . . . . . . . .165
Fig 41. Texas Instruments synchronous serial frame format:
a) single frame transfer and b)
continuous/back-to-back two frames.. . . . . . . . .168
Fig 42. Motorola SPI frame format with CPOL=0 and
CPHA=0 ( a) single transfer and b) continuous
transfer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169
Fig 43. Motorola SPI frame format (single transfer) with
CPOL=0 and CPHA=1. . . . . . . . . . . . . . . . . . . .170
Fig 44. SPI frame format with CPOL = 1 and CPHA = 0 ( a)
single and b) continuous transfer) . . . . . . . . . . .171
Fig 45. Motorola SPI frame format with CPOL = 1 and
CPHA = 1 (single transfer). . . . . . . . . . . . . . . . .172
Fig 46. Microwire frame format (single transfer) . . . . . .173
Fig 47. Microwire frame format (continuos transfers). . .174
Fig 48. Microwire frame format (continuos transfers) -
details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174
Fig 49. Sample PWM waveforms with a PWM cycle length
of 100 (selected by MR3) and MAT3:0 enabled as
PWM outputs by the PWCON register. . . . . . . .197
Fig 50. A timer cycle in which PR=2, MRx=6, and both
interrupt and reset on match are enabled . . . . .198
Fig 51. A timer cycle in which PR=2, MRx=6, and both
interrupt and stop on match are enabled . . . . . .198
Fig 52. Timer0/1 block diagram . . . . . . . . . . . . . . . . . . .199
Fig 53. Sample PWM waveforms with a PWM cycle length
of 100 (selected by MR3) and MAT3:0 enabled as
PWM outputs by the PWCON register. . . . . . . .210
Fig 54. A timer cycle in which PR=2, MRx=6, and both
interrupt and reset on match are enabled . . . . .210
Fig 55. A timer cycle in which PR=2, MRx=6, and both
interrupt and stop on match are enabled . . . . . .211
Fig 56. Timer2/3 block diagram . . . . . . . . . . . . . . . . . . .212
Fig 57. RTC block diagram . . . . . . . . . . . . . . . . . . . . . .213
Fig 58. RTC prescaler block diagram. . . . . . . . . . . . . . .222
Fig 59. RTC 32 kHz crystal oscillator circuit . . . . . . . . .224
Fig 60. Watchdog block diagram . . . . . . . . . . . . . . . . . . 228
Fig 61. Map of lower memory after reset for LPC2103 with
32 kB of Flash memory . . . . . . . . . . . . . . . . . . . 230
Fig 62. Boot process flowchart . . . . . . . . . . . . . . . . . . . 233
Fig 63. IAP Parameter passing . . . . . . . . . . . . . . . . . . . 244
Fig 64. EmbeddedICE debug environment block
diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
Fig 65. Waveforms for normal operations (not in debug
mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
Fig 66. Waveforms for debug mode using the primary JTAG
pins.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
Fig 67. RealMonitor components . . . . . . . . . . . . . . . . . 255
Fig 68. RealMonitor as a state machine . . . . . . . . . . . . 256
Fig 69. Exception handlers . . . . . . . . . . . . . . . . . . . . . . 259