Because RFL™ and Hubbell® have a policy of continuous product improvement, we reserve the right to change designs and specifications without notice.
RFL 9785 RFL Electronics Inc.
July 26, 2007
16-5 (973) 334-3100
16.4 THEORY OF OPERATION
A block diagram of the RFL 9785 Checkback Module appears in Figure 16-6. Figure 16-20 is a
component locator drawing and Figure 16-21 is a schematic diagram.
16.4.1 CPU AND MEMORY
U5 is the central processing unit (CPU) for the RFL 9785 Checkback Module. Its clock source is a 12-
MHz oscillator formed from crystal Y2 and capacitors C26 and C27. A 64K EPROM U6, is used to
store all program memory used by the CPU. An 8K static RAM U7, is used to store all user-entered
operating parameters and system variables. A lithium battery inside U7 guards against data loss during
power outages.
16.4.2 CPU I/O PORTS
CPU U5 has four I/O ports: Port 0 through Port 3.
Port 0 serves as a multiplexed, low-order address/data bus interface. During program memory fetches
and data or I/O read/write operations, Port 0 first outputs the low-order address byte. It then reads or
outputs the data byte to the bus (AD0 through AD7).
Port 1 is a general-purpose I/O interface. It is configured to input and output data and control signals to
the Checkback Module. Port lines P1.0 through P1.3 are outputs, and P1.4 through P1.7 are inputs.
Line P1.0 toggles at the end of each program pass to reset watchdog timer U3. Lines P1.1, P1.2 and
P1.3 are row enable outputs for the front-panel pushbutton switch matrix. They pull low in sequence to
enable each row of switches. Line P1.4, P1.5 and P1.6 are the column inputs for the 3 x 3 pushbutton
switch matrix. These inputs are read when each row is enabled to determine which push button has
been pressed. Line P1.7 is a spare input, whose state is determined by the position of strap J6.
Port 2 serves as the high-order address bus interface. During program memory fetches and data or I/O
read/write operations, Port 2 outputs the high-order address byte to the bus (A8 through A15).
Port 3 serves as an interface for several of the special features incorporated into the CPU. Line P3.0 is
the Receive Data (RXD) input for U5’s serial port, used for Head Slave/Slave communications. Line
P3.1 is the Transmit Data (TXD) output for U5’s serial port, which utilizes Mode 3 operation for Head
Slave/Slave communications. It has one start bit, eight data bits, one parity bit, and one stop bit, at
9600 bps. Line P3.2 is the Communications Interrupt (/COMINT) input, generated when DUART U1
requires servicing. Line P3.6 is the write (/WR) output, line P3.7 is the read (/RD) output, and lines
P3.3, P3.4, and P3.5 are not used in this application.
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