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RFL 9785 - Figure 16-6. Block Diagram, RFL 9785 Checkback Module

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Because RFL and Hubbell® have a policy of continuous product improvement, we reserve the right to change designs and specications without notice.
RFL 9785 RFL Electronics Inc.
July 26, 2007
16-7 (973) 334-3100
Figure 16-6. Block diagram, RFL 9785 Checkback module
8K RAM
U7
AD0 -AD7
A0 -A12
64K ROM
U6
AD0 -AD7
A0 -A15
DUART
U1
START
STOP
RESERVE
TX FAIL
BLOCK OUT
RMT INIT
EX
IN
TERNAL
PUTS
AD0 -AD7
A0 –A3
DISPLAY SELECT
START TEST
RESET LOG
UP
DOWN
HC1
HC2
HC3
HC4
WATCHDOG
TIMER
U3
MICRO-
PROCESSOR
U5
LATCH
A0 - A7
AD0 - AD7
A8 - A15
CONTROL
DIODE
MATRIX
CR8 - CR14
TXD
RXD
HEAD SLAVE/SLAVE
COMMUNICATIONS
DTR
RTS
TxD
RxD
CTS
RS-232
PORT
RS-232
INTERFACE
U4
FRONT
PANEL
SWI
TCH
INPUTS
DECODER
LATCH LATCH
SHIFT
REGISTER
LATCH
TO 7-
SEGMENT
LED DISPLAYS
CLK OUT
SR OUT
TEST IN PROGRESS
CHKBKLEV
TEST OUT
CHKBK
TO PASS/FAIL
ANNUNCI
ATORS
TO LED
ANNUNCI
ATORS
DRIVER
DRIVER
A0 -A2 AD0 - AD7
P/O XILINX
U2
P/O XILINX
U2
/2
/7

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