701 Motor Protection Relay Date Code 20010719
SEL
OGIC
®
Control Equations & Relay Logic
Latch Control Switch Settings
B.18
Latch Control Switch States Are Retained During Power Loss
The states of the latch bits are retained if power to the relay is lost and then
restored. This capability makes the latch bit feature behave the same as traditional
latching relays.
Make Latch Control Switch Settings With Care
The latch bit states are stored in nonvolatile memory so they can be retained
during power loss. The nonvolatile memory is rated for a finite number of writes for all
cumulative latch bit state changes. Exceeding the limit can result in an EEPROM
self-test failure. An average of 150 cumulative latch bit state changes per day can be
made for a 25-year relay service life.
The SEL
OGIC control equation settings SETn and RSTn for any given latch bit
LTn (n = 1–4; see Figure B.5 on page B.17) must be set with care. Settings SETn and
RSTn must not result in continuous cyclical operation of latch bit LTn. Use timers to
qualify conditions set in settings SETn and RSTn.
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