Logic
Figure 2-98 shows the logic diagram for the breaker failure protection with the thermal stage and the definite
time Ι2>> stage. The Ι2> stage is not represented. It is available in this operating mode, but is generally not
required because an own warning level is available. The protection may be blocked via a binary input. That
way, pickups and time stages are reset. The content of the thermal replica can be emptied via the binary input
>RM th.rep. I2
and
>BLOCK I2
.
When leaving the work area of the negative sequence protection (all phase currents under the minimum
current setting PoleOpenCurr. for the concerned measuring location or side or at least one phase current is
greater than 4 · Ι
N
) .
[logikdia-schieflastschutz-termstufe, 1, en_GB]
Figure 2-98
Logic diagram of the asymmetrical load protection - illustrated for the thermal stage with I>>
stage (simplified)
Functions
2.8 Unbalanced Load Protection
192 SIPROTEC 4, 7UT6x, Manual
C53000-G1176-C230-5, Edition 09.2016
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