Preface
vi 7SA6 Manual
C53000-G1176-C133-1
I
ph
>
,SK!!
0T
S
R
Q
≥1
Dynamic input signals
Creation of an analog output signal
out of several analog input signals
Timing element (resetting time delay)
Monitoring stage with
parameter address and parameter name
T
Transition-operated timing element
Static memory (RS–flipflop) with Set
=1
Exclusive
OR
(Non-equivalence): output active, if
only
one
of the inputs is active
=
Coincidence: output active, if
both
inputs
are active in the same direction
0T
7,SK!!
Timing element (pickup delay) with
Input (S), Reset Input (R), Output (Q)
and Negated Output (Q
)
Q
with action time T
parameter address and parameter name
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