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Anritsu MS2024B - Page 29

Anritsu MS2024B
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VNA Fundamentals 3-3 VNA Master Architecture
Vector Network Analyzer MG PN: 10580-00289 Rev. K 3-5
Figure 3-3 shows a general block diagram of the three-receiver architecture that is used in
the MS20xxB VNA Master and the S412E LMR Master and shows how the S-parameters are
related to the signals that are being transmitted and received by the ports.
Figure 3-3. MS20xxB VNA Master and S412E LMR Master Block Diagram
DUT
Port 1 Port 2
Receiver
Port 1
Reference
Receiver
Bridge/
Coupler
S
11
S
21
Receiver
Port 2
Source

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