Table Of Contents
Paragraph Page
Number Number
MPC5200B Users Guide, Rev. 1
TOC-12 Freescale Semiconductor
14.5.17 FEC Descriptor Individual Address 2 Register—MBAR + 0x311C ..............................................................14-24
14.5.18 FEC Descriptor Group Address 1 Register—MBAR + 0x3120 .....................................................................14-25
14.5.19 FEC Descriptor Group Address 2 Register—MBAR + 0x3124 .....................................................................14-25
14.5.20 FEC Tx FIFO Watermark Register—MBAR + 0x3144 .................................................................................14-26
14.6 FIFO Interface .......................................................................................................................................................14-27
14.6.1 FEC Rx FIFO Data Register—MBAR + 0x3184 ...........................................................................................14-28
14.7 FEC Tx FIFO Data Register—MBAR + 0x31A4................................................................................................. 14-28
14.7.1 FEC Rx FIFO Status Register—MBAR + 0x3188 .........................................................................................14-28
14.8 FEC Tx FIFO Status Register—MBAR + 0x31A8 ...............................................................................................14-28
14.8.1 FEC Rx FIFO Control Register—MBAR + 0x318C ......................................................................................14-29
14.8.2 FEC Rx FIFO Last Read Frame Pointer Register—MBAR + 0x3190 ...........................................................14-30
14.8.3 FEC Rx FIFO Last Write Frame Pointer Register—MBAR + 0x3194 ..........................................................14-31
14.8.4 FEC Rx FIFO Alarm Pointer Register—MBAR + 0x3198 ............................................................................14-31
14.8.5 FEC Rx FIFO Read Pointer Register—MBAR + 0x319C .............................................................................14-32
14.8.6 FEC Rx FIFO Write Pointer Register—MBAR + 0x31A0 ............................................................................14-33
14.8.7 FEC Reset Control Register—MBAR + 0x31C4 ...........................................................................................14-33
14.8.8 FEC Transmit FSM Register—MBAR + 0x31C8 ..........................................................................................14-34
14.9 Initialization Sequence ..........................................................................................................................................14-34
14.9.1 Hardware Controlled Initialization .................................................................................................................14-34
14.9.2 User Initialization (Prior to Asserting ETHER_EN) ......................................................................................14-35
14.9.2.1 Microcontroller Initialization ...................................................................................................................14-35
14.9.3 Frame Control/Status Words ..........................................................................................................................14-35
14.9.3.1 Receive Frame Status Word .....................................................................................................................14-35
14.9.3.2 Transmit Frame Control Word .................................................................................................................14-36
14.9.4 Network Interface Options ..............................................................................................................................14-36
14.9.5 FEC Frame Reception .....................................................................................................................................14-37
14.9.6 Ethernet Address Recognition ........................................................................................................................14-37
14.9.7 Full-Duplex Flow Control ...............................................................................................................................14-42
14.9.8 Inter-Packet Gap Time ....................................................................................................................................14-43
14.9.9 Collision Handling ..........................................................................................................................................14-43
14.9.10 Internal and External Loopback ......................................................................................................................14-44
14.9.11 Ethernet Error-Handling Procedure ................................................................................................................14-44
14.9.11.1 Transmission Errors ..................................................................................................................................14-44
14.9.11.2 Reception Errors .......................................................................................................................................14-44
Chapter 15 Programmable Serial Controllers (PSC)
15.1 Overview .................................................................................................................................................................15-1
15.1.1 PSC Functions Overview ..................................................................................................................................15-1
15.1.2 Features .............................................................................................................................................................15-2
15.2 PSC Registers—MBAR + 0x2000, 0x2200, 0x2400, 0x2600, 0x2800, 0x2C00 ...................................................15-3
15.2.1 Mode Register 1 (0x00)—MR1 ........................................................................................................................15-5
15.2.2 Mode Register 2 (0x00) — MR2 ......................................................................................................................15-6
15.2.3 Status Register (0x04) — SR ............................................................................................................................15-7
15.2.4 Clock Select Register (0x04) — CSR .............................................................................................................15-11
15.2.5 Command Register (0x08)—CR .....................................................................................................................15-11
15.2.6 Rx Buffer Register (0x0C) — RB ..................................................................................................................15-13
15.2.7 Tx Buffer Register (0x0C)—TB .....................................................................................................................15-15
15.2.8 Input Port Change Register (0x10) — IPCR ..................................................................................................15-16
15.2.9 Auxiliary Control Register (0x10) — ACR ....................................................................................................15-17
15.2.10 Interrupt Status Register (0x14) — ISR ..........................................................................................................15-18
15.2.11 Interrupt Mask Register (0x14)—IMR ...........................................................................................................15-18
15.2.12 Counter Timer Upper Register (0x18)—CTUR .............................................................................................15-19
15.2.13 Counter Timer Lower Register (0x1C)—CTLR .............................................................................................15-20
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