Table of Contents
Paragraph Page
Number Number
MPC5200B Users Guide, Rev. 1
Freescale Semiconductor TOC-13
15.2.14 Codec Clock Register (0x20)—CCR ..............................................................................................................15-21
15.2.15 Interrupt Vector Register (0x30)—IVR ..........................................................................................................15-23
15.2.16 Input Port Register (0x34)—IP .......................................................................................................................15-23
15.2.17 Output Port 1 Bit Set (0x38)—OP1 ................................................................................................................15-24
15.2.18 Output Port 0 Bit Set (0x3C)—OP0 ...............................................................................................................15-24
15.2.19 Serial Interface Control Register (0x40)—SICR ............................................................................................15-25
15.2.20 Infrared Control 1 (0x44)—IRCR1 ................................................................................................................15-27
15.2.21 Infrared Control 2 (0x48)—IRCR2 ................................................................................................................15-28
15.2.22 Infrared SIR Divide Register (0x4C)—IRSDR ..............................................................................................15-29
15.2.23 Infrared MIR Divide Register (0x50)—IRMDR ............................................................................................15-30
15.2.24 Infrared FIR Divide Register (0x54)—IRFDR ..............................................................................
.................15-31
15.2.25 Rx FIFO Number of Data (0x58)—RFNUM .................................................................................................15-33
15.2.26 Tx FIFO Number of Data (0x5C)—TFNUM .................................................................................................15-33
15.2.27 Rx FIFO Data (0x60)—RFDATA ..................................................................................................................15-33
15.2.28 Rx FIFO Status (0x64)—RFSTAT .................................................................................................................15-33
15.2.29 Rx FIFO Control (0x68)—RFCNTL ..............................................................................................................15-34
15.2.30 Rx FIFO Alarm (0x6E)—RFALARM ............................................................................................................15-34
15.2.31 Rx FIFO Read Pointer (0x72)—RFRPTR ......................................................................................................15-35
15.2.32 Rx FIFO Write Pointer(0x76)—RFWPTR .....................................................................................................15-35
15.2.33 Rx FIFO Last Read Frame (0x7A)—RFLRFPTR ..........................................................................................15-35
15.2.34 Rx FIFO Last Write Frame PTR (0x7C)—RFLWFPTR ................................................................................15-36
15.2.35 Tx FIFO Data (0x80)—TFDATA .............................................................................................
.....................15-36
15.2.36 Tx FIFO Status (0x84)—TFSTAT .................................................................................................................15-36
15.2.37 Tx FIFO Control (0x88)—TFCNTL ..............................................................................................................15-37
15.2.38 Tx FIFO Alarm (0x8E)—TFALARM ............................................................................................................15-37
15.2.39 Tx FIFO Read Pointer (0x92)—TFRPTR ......................................................................................................15-37
15.2.40 Tx FIFO Write Pointer (0x96)—TFWPTR ....................................................................................................15-38
15.2.41 Tx FIFO Last Read Frame (0x9A)—TFLRFPTR ..........................................................................................15-38
15.2.42 Tx FIFO Last Write Frame PTR (0x9C)—TFLWFPTR ................................................................................15-38
15.3 PSC Operation Modes ...........................................................................................................................................15-39
15.3.1 PSC in UART Mode .......................................................................................................................................15-39
15.3.1.1 Block Diagram and Signal Definition for UART Mode ..........................................................................15-39
15.3.1.2 UART Clock Generation ..........................................................................................................................15-41
15.3.1.3 Transmitting in UART Mode ...................................................................................................................15-41
15.3.1.4 Receiver in UART Mode ..........................................................................................................................15-42
15.3.1.5 Configuration Sequence for UART Mode ................................................................................................15-43
15.3.2 PSC in Codec Mode ........................................................................................................................................15-44
15.3.2.1 Block Diagram and Signal Definition for Codec Mode ...........................................................................15-45
15.3.2.2 Codec Clock and Frame Generation .........................................................................................................15-46
15.3.2.2.1 BitClk and Frame in “normal” Codec and I2S Mode ........................................................................15-47
15.3.2.2.2 BitClk and Frame in “Cell Phone” Mode ..........................................................................................15-47
15.3.2.2.3 BitClk and Frame in SPI Mode ..........................................................................................................15-48
15.3.2.3 Transmitting and Receiving in Codec Mode ............................................................................................15-49
15.3.2.4 Configuration Sequence Examples for Codec Modes ..............................................................................15-50
15.3.2.4.1 PSC1 in 16-bit “soft Modem” Slave Mode ..............................................................................
..........15-50
15.3.2.4.2 PSC2 in 32-bit “soft Modem” Master Mode ......................................................................................15-51
15.3.2.4.3 PSC 1 in Cell Phone Master Mode, PSC2 is Cell Phone Slave .........................................................15-51
15.3.2.4.4 PSC2 in SPI Slave Mode ....................................................................................................................15-52
15.3.2.4.5 PSC3 in SPI Master Mode .................................................................................................................15-53
15.3.2.4.6 PSC1 in I2S Master Mode ..................................................................................................................15-54
15.3.3 PSC in AC97 Mode ........................................................................................................................................15-55
15.3.3.1 Block Diagram and Signal Definition for AC97 Mode ............................................................................15-56
15.3.3.2 Transmitting and Receiving in AC97 Mode .............................................................................................15-57
15.3.3.3 AC97 Low-Power Mode ..........................................................................................................................15-57
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