Freescale Semiconductor MPC5200B - Page 32

List of Tables
Table Page
Number Number
MPC5200B Users Guide, Rev. 1
Freescale Semiconductor LOT-9
18-5 I
2
C Control Register ................................................................................................................................................18-7
18-6 I
2
C Status Register ..................................................................................................................................................18-8
18-7 I
2
C Data I/O Register ............................................................................................................................................18-10
18-8 I
2
C Interrupt Control Register ...............................................................................................................................18-10
19-1 MSCAN Register Organization ...............................................................................................................................19-3
19-2 Module Memory Map .............................................................................................................................................19-4
19-3 MSCAN Control Register 0 ....................................................................................................................................19-5
19-4 MSCAN Control Register 1 ....................................................................................................................................19-6
19-5 MSCAN Bus Timing Register 0 .............................................................................................................................19-8
19-6 Baud Rate Prescaler .................................................................................................................................................19-8
19-7 MSCAN Bus Timing Register 1 .............................................................................................................................19-8
19-8 Time Segment 1 Values ..........................................................................................................................................19-9
19-9 Time Segment 2 Values ..........................................................................................................................................19-9
19-10 MSCAN Receiver Flag Register ...........................................................................................................................19-10
19-11 MSCAN Receiver Interrupt Enable Register ........................................................................................................19-11
19-12 MSCAN Transmitter Flag Register .......................................................................................................................19-12
19-13 MSCAN Transmitter Interrupt Enable Register ....................................................................................................19-13
19-14 MSCAN Transmitter Message Abort Request Register ........................................................................................19-13
19-15 MSCAN Transmitter Message Abort Acknowledgement Register ......................................................................19-14
19-16 MSCAN Transmit Buffer Selection Register ........................................................................................................19-14
19-17 MSCAN ID Acceptance Control Register ............................................................................................................19-15
19-18 Identifier Acceptance Hit Indication .....................................................................................................................19-15
19-19 Identifier Acceptance Mode Settings ....................................................................................................................19-15
19-20 MSCAN Receive Error Counter Register .............................................................................................................19-16
19-21 MSCAN Transmit Error Counter Register ............................................................................................................19-16
19-22 MSCAN ID Acceptance Registers (1st Bank) ......................................................................................................19-17
19-23 MSCAN ID Acceptance Registers (2nd Bank) .....................................................................................................19-18
19-24 MSCAN ID MaskRegisters (1st Bank) .................................................................................................................19-19
19-25 MSCAN ID MaskRegisters (2nd Bank) ................................................................................................................19-20
19-26 Message Buffer Organization ................................................................................................................................19-21
19-27 Receive / Transmit Message Buffer Extended Identifier ......................................................................................19-21
19-28 Standard Identifier Mapping .................................................................................................................................19-22
19-29 Data Length Codes ................................................................................................................................................19-24
19-30 MSCAN Transmit Buffer Priority Register ..........................................................................................................19-24
19-31 MSCAN Time Stamp Register (High Byte) ..........................................................................................................19-24
19-32 MSCAN Time Stamp Register (Low Byte) ..........................................................................................................19-25
19-33 Time Segment Syntax ...........................................................................................................................................19-32
19-34 CAN Standard Compliant Bit Time Segment Settings .........................................................................................19-32
19-35 CPU vs. MSCAN Operating Modes ......................................................................................................................19-33
20-1 Module Memory Map .............................................................................................................................................20-5
20-2 BDLC Control Register 1 ........................................................................................................................................20-6
20-3 BDLC State Vector Register ...................................................................................................................................20-7
20-4 BDLC Control Register 2 ........................................................................................................................................20-8
20-5 BDLC Data Register .............................................................................................................................................20-12
20-6 BDLC Analog Round Trip Delay Register ...........................................................................................................20-13
20-7 BARD Values vs. Transceiver Delay and Transmitter Timing Adjustment .........................................................20-13
20-8 BDLC Rate Select Register ...................................................................................................................................20-14
20-9 BDLC Rate Selection for Binary Frequencies [CLKS = 1] ..................................................................................20-15
20-10 BDLC Rate Selection for Integer Frequencies [CLKS = 0] ..................................................................................20-15
20-11 BDLC Control Register .........................................................................................................................................20-15
20-12 BDLC Status Register ...........................................................................................................................................20-16
20-13 BDLC Transmitter VPW Symbol Timing for Integer Frequencies ......................................................................20-19
20-14 BDLC Transmitter VPW Symbol Timing for Binary Frequencies .......................................................................20-20
20-15 BDLC Receiver VPW Symbol Timing for Integer Frequencies ...........................................................................20-20