Microsemi IGLOO2 - 2 Board Design Guidelines for Smartfusion2 Soc and IGLOO2 Fpgas; Design Considerations; Power Supplies

Board Design Guidelines for SmartFusion2 SoC and IGLOO2 FPGAs
AC393 Application Note Revision 14.0 4
2 Board Design Guidelines for SmartFusion2
SoC and IGLOO2 FPGAs
This application note provides board-level design guidelines for SmartFusion
®
2 and IGLOO
®
2 devices.
This document can be used along with the Layout Guidelines for SmartFusion2- and IGLOO2-Based
Board Design, page 38 that describes the PCB design. These guidelines must be treated as a
supplement to standard board-level design practices.
Good board design practices are required to obtain expected performance from both PCB and
SmartFusion2/IGLOO2 devices. High quality and reliable results depend on minimizing noise levels,
preserving signal integrity, meeting impedance and power requirements, and using appropriate SerDes
protocols.
This document assumes that the reader has a good understanding of the SmartFusion2/IGLOO2 device,
is experienced in digital and analog board design, and knows about the electrical characteristics of
systems. Background information on the key theories and concepts of board-level design is available in
High Speed Digital Design: A Handbook of Black Magic, and other industry literature.
2.1 Design Considerations
The SmartFusion2/IGLOO2 device supports various high-speed interfaces using both double data rate
input/output (DDRIO) and SerDes I/O. DDRIO is a multi-standard I/O optimized for low-power DDR,
DDR2, and DDR3 performance. SerDes I/O are dedicated to high-speed serial communication protocols.
The SerDes I/O supports protocols such as PCI Express 2.0, 10 Gbps attachment unit interface (XAUI),
serial gigabit media independent interface (SGMII), JESD204B, and user-defined high-speed serial
protocol implementation in fabric.
Routing high-speed serial data over a PCB is a challenge as losses, dispersion, and crosstalk effects
increase with speed. Channel losses and crosstalk decrease the signal-to-noise ratio and limit the data
rate on the channel.
Subsequent sections discuss the following:
• Power supplies
• Limiting surge current during device reset
• Clocks
• Reset circuit
•JTAG
• Special pins
• Device programming
•SerDes
• LPDDR, DDR2, and DDR3
• User I/O and clock pins
• Achieving a two-rail design
•SerDes
• Brownout detection (BOD)
To verify the design, see the CL0034: SmartFusion2/IGLOO2 Hardware Board Design Checklist.
2.2 Power Supplies
The following figure illustrates the typical power supply requirements, including PLL RC filter values, for
SmartFusion2/IGLOO2 devices. For more information about decoupling capacitors associated with
individual power supplies, see Table 2, page 7.