Layout Guidelines for SmartFusion2- and IGLOO2-Based Board Design
AC393 Application Note Revision 14.0 38
3 Layout Guidelines for SmartFusion2- and
IGLOO2-Based Board Design
This chapter provides guidelines for the hardware board layout that incorporates SmartFusion2 SoC
FPGA or IGLOO2 FPGA devices. Good board layout practices are required to achieve the expected
performance from the printed circuit boards (PCB) and SmartFusion2/IGLOO2 devices. These are
essential to achieve high quality and reliable results such as low-noise levels, signal integrity, impedance,
and power requirements. The guidelines mentioned in this document act as a supplement to the
standard board-level layout practices.
This chapter assumes that the users have a good understanding of the SmartFusion2/IGLOO2 chip,
experience in digital and analog board layout, and knowledge of transmission line theory and signal
integrity. For more information about the recommended guidelines for designing
SmartFusion2/IGLOO2-based boards, see Board Design Guidelines for SmartFusion2 SoC and IGLOO2
FPGAs, page 4.
Note: The target impedance calculated in this document is with respect to the development board. The
simulations show the impedance that meets the target impedance of the development board. The target
impedance depends on the logic implemented on SmartFusion2/IGLOO2; hence Microsemi
recommends calculating the target impedance of the board.
3.1 Power Supply
In power supply design, it is important to know the target impedance of the power planes. The target
impedance varies depending on the design. This helps in planning the requirement of the number of
decoupling capacitors based on the target impedance. The number of decoupling capacitors varies
based on the design.
Complex FPGA designs have increasing amounts of current transients switching across the power bus.
Simultaneously switching outputs (SSO) contribute a major share of instantaneous current issues.
Decoupling is necessary to prevent the instantaneous currents. Decoupling is only effective when
inductance is minimized. Low inductance decoupling provides localized high frequency energy to
decouple noise from the switching currents of the device power bus. This is most effective when
capacitors are in close proximity to the device. Some of these high-frequency de-coupling capacitors
must be placed directly under the FPGA or on single side. These capacitors must be placed close to the
power and ground pins of the device and routed with thick trace.
To calculate the number of decoupling capacitors, it is important to know the target impedance of the
power plane. Target impedance is calculated as follows:
Where,
V
supply
: Supply voltage of the power plane.
% Ripple: % of ripples allowed on the power plane; see DS0128: IGLOO2 and SmartFusion2 Datasheet
for more information about ripple in Recommended Operating Conditions table.
I
trans
: Transient current drawn on the power plane. Generally, the transient current is half of the
maximum current. Maximum current is taken from the power calculator sheet.
Z
max
: Target impedance of the plane.
Z
Max
Ripple%
V
supply
I
trans
------------------
×=
To Next Page
Loading...
