Board Design Guidelines for SmartFusion2 SoC and IGLOO2 FPGAs
AC393 Application Note Revision 14.0 28
2.8.3 SerDes Reference Clock Requirements
The selection of the reference clock source or clock oscillator is driven by many parameters such as
frequency range, output voltage swing, jitter (deterministic, random, and peak-to-peak), rise and fall
times, supply voltage and current, noise specification, duty cycle and duty cycle tolerance, and frequency
stability.
For SerDes reference clock pins, the internal ODT option should be enabled, and therefore, external
termination is not required.
Following are the requirements for the SerDes reference clock:
• Must be within the range of 100 MHz to 160 MHz.
• Must be within the tolerance range of the I/O standard.
• The input clock for PCIe is typically a 100 MHz reference clock provided by the host slot for an end
point device through the PCIe connector of the motherboard. If two components connected through
the PCIe bus use the same 100 MHz clock source, it is called common clock mode. In any other
case, the PCIe device is in separated clock mode where one component either does not use a 100
MHz reference clock or uses a 100 MHz reference clock that does not have the same source and
phase as the one used by the connected component.
See the PCI Express Base specification Rev 2.1 for detailed PHY specifications. Also see the PCIe Add-
in Card Electro-Mechanical (CEM) specifications.
2.8.4 PLL Filter
To obtain a reasonable level of long-term jitter, it is vital to supply the PLL with analog-grade power.
Typically, an RC or RLC filter is used, where C is composed of multiple devices to obtain a wide spectrum
of noise absorption. Although the circuit is simple, its effectiveness depends on specific board layout
requirements. See Figure 1, page 5 for an illustration of a typical power supply connection.
• The DC series resistance of this filter should be limited. Microsemi recommends limiting the voltage
drop across this device to less than 5% under worst-case conditions.
• Place a main ceramic or tantalum capacitor (see Figure 1, page 5), in the filter design to obtain good
low-frequency cut-off. At least one low equivalent series inductance (ESL) and low ESR capacitor in
parallel (~0.1 µF ceramic capacitor in 0402 package) enables the filter to maintain its attenuation
through moderately high frequencies.
• The package ball grid array (BGA) pattern allows the placement of 0402 or 0201 components across
the SERDES_x_Lyz_VDDAPLL and SERDES_x_Lyz_REFRET pins on the backside of the board.
• For the SerDes block, SERDES_x_Lyz_REFRET serves as the local on-chip ground return path for
SERDES_x_Lyz_VDDAPLL. Therefore, the external board ground must not get shorted with
SERDES_x_Lyz_REFRET under any circumstances.
• High-quality series inductors must not be used without a series resistor when there is a high-gain
series resonator. In general, avoid using inductive chokes in any supply path unless care is taken to
manage resonance.
See Figure 1, page 5 for SerDes analog power connections. A high-precision 1.2 KΩ, 1% resistor in
either a 0402 or 0201 package is required for the external reference resistor connected between
SERDES_x_Lyz_REXT and SERDES_x_Lyz_REFRET.
2.9 LPDDR, DDR2, and DDR3
DDRIO is a multi-standard I/O buffer optimized for LPDDR, DDR2, and DDR3 performance.
SmartFusion2/IGLOO2 devices include two DDR subsystems: the fabric DDR controllers (FDDR) and
microcontroller subsystem (MSS) DDR (MDDR) controllers. All DDRIO can be configured as differential
I/O or two single-ended I/O. DDRIO can be connected to the respective DDR sub-system PHYs or can
be used as user I/O.
For more information on FDDR and MDDR, see the SmartFusion2 FPGA Fabric DDR Controller
Configuration Guide and SmartFusion2 MSS DDR Controller Configuration Guide.
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