Microsemi IGLOO2 - Obtaining a Two-Rail Design for Non-Serdes Applications; Operating Voltage Rails; Table 19 Operating Voltage Rails

Board Design Guidelines for SmartFusion2 SoC and IGLOO2 FPGAs
AC393 Application Note Revision 14.0 35
2.11 Obtaining a Two-Rail Design for Non-SerDes
Applications
SmartFusion2/IGLOO2 devices require multiple power supplies for functional operation, programming,
and high-speed serial interfaces. It is possible to design an application with only two voltage rails using
SmartFusion2/IGLOO2 devices.
I/O banks in SmartFusion2 and IGLOO2 devices support a wide range of I/O standards. I/O bank
supplies can operate at +1.2 V, +1.5 V, +1.8 V, +2.5 V, or +3.3 V. To obtain a two-voltage-rail design, the
core voltage should be connected to +1.2 V, and the mandatory I/O bank supplies and VPP supplies can
be connected to +2.5 V or +3.3 V.
2.11.1 Operating Voltage Rails
SmartFusion2/IGLOO2 devices require +1.2 V for the core supply and either +2.5 V or +3.3 V for I/O and
analog supplies. The following table lists operating voltage requirements for the devices.
Table 19 • Operating Voltage Rails
Pin Name Description Operating Voltage
VDD DC core supply voltage. +1.2 V
VDDIx
1
1. The 3.3 V supply can be connected to MSIO VDDIx bank only.
I/O bank supply. +1.2 V, +1.5 V, +1.8 V,
+2.5 V, or +3.3 V
SERDES_x_VDD PCIe/PCS supply. +1.2 V
SERDES_x_L[01/23]_VDDAIO Tx/Rx analog I/O voltage. Low-voltage power for lanes
0, 1, 2, and 3 of the SerDes interface.
+1.2 V
VPP
2
2. For M2S090T(S), M2S150T(S) devices, VPP, and VPPNVM must be connected to +3.3 V.
Power supply for charge pump. +2.5 V or +3.3 V
VPPNVM
1
Analog sense-circuit supply for the embedded non-
volatile memory (eNVM).
+2.5 V or +3.3 V
CCC_xyz_PLL_VDDA Analog power pad for CCC PLL. +2.5 V or +3.3 V
MSS/HPMS_xDDR_PLL_VDDA Analog power pad for xDDR PLL. +2.5 V or +3.3 V
SERDES_x_PLL_VDDA High supply voltage for SerDes PLL. +2.5 V or +3.3 V
SERDES_x_L[01/23]_VDDAPLL Analog power for SerDes PLL of lanes 0, 1, 2, and 3. +2.5 V