Microsemi IGLOO2 - I;O Glitch in a Blank Device; Power Supply Flow

Board Design Guidelines for SmartFusion2 SoC and IGLOO2 FPGAs
AC393 Application Note Revision 14.0 12
To minimize I/O glitch during power-down, any one of the following solutions can be used:
• The device must enter Flash*Freeze mode before a device reset asserted.
• In the power-down sequence, VDDI must be powered-down first and then the DEVRST_N must be
asserted.
• An external pull-down resistor (for example 1K resistor) must be used for the I/O.
• Critical outputs must be driven high before the DEVRST_N assertion.
2.3.3 I/O Glitch in a Blank Device
I/O glitch was observed on bank 2 of a blank device before programming. On a blank device, the I/Os are
placed in the Flash*Freeze state (tristate with weak pull-ups). When the programming starts, the I/Os
transition to the boundary scan mode. On I/O bank 2, there is a race condition between exiting the
Flash*Freeze mode and the entering boundary scan mode. During this transition, the outputs on bank 2
briefly drive high until the boundary scan mode is enabled. This transition results in an I/O glitch.
To prevent this glitch, use the JTAG command to adjust the I/O drive strength to zero before
programming starts.
2.3.3.1 Application Impact Due to Glitch
Application Impact: There is no reliability impact because the duration of the I/O glitch does not exceed
the datasheet overshoot specifications. The glitch amplitude tracks the VDDI bank voltage and rises
slightly above the VDDI. For example, at 3.3 V of VDDI, the glitch rises above 3.3 V by approximately 0.3
V for 5 ns. The the glitch amplitude is directly proportional to the VDDI value.
Resolution: Regenerate the bitstream using Libero 11.8 SP1.
2.3.4 Power Supply Flow
SmartFusion2/IGLOO2 FPGA devices require multiple power supplies. Figure 3, page 13 illustrates a
topology for generating the required power supplies from a single 12 V source. This example power
supply topology is based on SmartFusion2 M2S050T-FG896 device with two SerDes channels
(SERDES0 and SERDES1) and a DDR3 interface.