Board Design and Layout Checklist
AC393 Application Note Revision 14.0 82
5 Board Design and Layout Checklist
This chapter provides a set of checks for designing hardware using Microsemi SmartFusion2 and
IGLOO2 FPGAs. The checklists provided in this chapter are a high-level summary to assist the design
engineers in the design process.
5.1 Prerequisites
Ensure that you have gone through the following chapters before reading this chapter:
• Board Design Guidelines for SmartFusion2 SoC and IGLOO2 FPGAs, page 4
• Layout Guidelines for SmartFusion2- and IGLOO2-Based Board Design, page 38
This checklist is intended as a guideline only. The SmartFusion2 and IGLOO2 families consists of
FPGAs ranging from densities of 6 K to 100 K logic elements (LE).
5.2 Design Checklist
The following table lists the checks that design engineers must take care of while designing the system.
Table 23 • Design Checklist
S.No. Checklist Yes/No
Prerequisites
1. Read datasheet and pin description user guides:
– IGLOO2 and SmartFusion2 Datasheet
– IGLOO2 Pin Descriptions
– SmartFusion2 Pin Descriptions
2. Check for available designs and development tools.
3. Refer to the board-level schematics of the SmartFusion2 Security Evaluation
Kit or SmartFusion2 Advanced Development Kit.
Design Specifications
4. Draw the high-level design with architectural block diagram including all the
basic interfaces.
5. Specify all the I/O interfaces for all banks in the FPGA.
6. Create a detailed functional verification test plan.
7. Check for IP software that impacts the system design.
Device Selection
8. Check for available device variants of the SmartFusion2 or IGLOO2 FPGA.
Select a device based on the I/O pin count, transceivers, microcontroller
subsystem (MSS) peripherals, phase-locked loops (PLLs), and speed grade.
9. Check device errata:
– SmartFusion2 Errata
– SmartFusion2 M2S150ES/M2S090ES Errata
– IGLOO2 Errata
10. Compare the design requirements with the available interfaces and number of
I/Os.
11. Estimate the required logic utilization, memory, number of I/O pins, and density.
To Next Page
Loading...