Layout Guidelines for SmartFusion2- and IGLOO2-Based Board Design
AC393 Application Note Revision 14.0 65
Note: The following guidelines are applicable for DDR2, DDR3, and LPDDR:
• Short the MDDR_TMATCH_0_IN and MDDR_TMATCH_0_OUT pins under BGA using short trace.
• Short the MDDR_TMATCH_1_IN and MDDR_TMATCH_1_OUT pins under BGA using short trace.
• Short the MDDR_TMATCH_ECC_IN and MDDR_TMATCH_ECC_OUT pins under BGA using short
trace.
• Short the FDDR_TMATCH_0_IN and FDDR_TMATCH_0_OUT pins under BGA using short trace.
• Short the FDDR_TMATCH_1_IN and FDDR_TMATCH_1_OUT pins under BGA using short trace.
• Short the FDDR_TMATCH_ECC_IN and FDDR_TMATCH_ECC_OUT pins under BGA using short
trace.
For more information about DDR2 and LPDDR memory layout guidelines, see the Micron Memory
Layout Guidelines in the following documents, available on the Micron website:
• TN-47-20: Hardware Tips for Point-to-Point System Design from Micron
• TN-46-19: Hardware Tips for Point-to-Point System Design from Micron
The following figure shows an example layout.
Figure 62 • TMATCH Signals (Example Layout)
3.10.3 Simulation Considerations
Simulations ensure that the DDR and controller meet timing requirements and also ensure that the
quality of the received waveform in terms of undershoot, overshoot and jitter and so on.
The following files are required for the DDR3 simulation:
• IBIS file of SmartFusion2/IGLOO2
• IBIS file of DDR3 memory
• PCB files of SmartFusion2/IGLOO2 board and DIMM, if used
• Connector models if DIMM is used
The following sections describe how to run the serial channel simulations.
3.10.3.1 Step 1: Gathering the Required Files
3.10.3.1.1 IBIS Models
To download the IBIS models of SmartFusion2/IGLOO2 and the IBIS-AMI models of DDR3 memory
which is going to interface with SmartFusion2/IGLOO2, see the following web pages on the Microsemi
website:
• www.microsemi.com/soc/download/ibis/SmartFusion2.aspx
• www.microsemi.com/soc/download/ibis/IGLOO2.aspx
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