Board Design Guidelines for SmartFusion2 SoC and IGLOO2 FPGAs
AC393 Application Note Revision 14.0 6
• VPPNVM: eNVM supply for the device. This pin must be connected to the VPP supply.
• VREFx: Reference voltage for MDDR/FDDR signals, which is powered through the corresponding
bank supply (VDDIx). Can be DNC or grounded (VSS) when unused.
• SERDES_x_VDD: The 1.2 V main power supply for the SerDes.SERDES_x_Lyz_VDDAIO: The
+1.2 V SerDes PMA supply for Tx/Rx analog I/O. The SerDes VDDAIO must be powered up/down at
the same voltage as the core VDD supply on the device.
• CCC_xyz_PLL_VDDA and MSS_xDDR_PLL_VDDA: If the associated PLL is used as a clock
multiplier, these supplies must be connected over the RC filter circuitry between the common PLL
supply and the corresponding on-board PLL return path. If the PLL is unused or used as a clock
divider, these supplies can be connected directly to either 2.5 V or 3.3 V without filter circuitry.
• SERDES_x_Lyz_REFRET: This pin provides the internal PLL current return path for
SERDES_x_Lyz_VDDAPLL. This pin must be connected to the corresponding SerDes VDDA PLL
through an RC filter circuit, as shown in Figure 1, page 5. For more information about unused pins,
see Figure 4, page 14.
• SERDES_x_PLL_VSSA: This pin provides the internal PLL current return path for
SERDES_x_PLL_VDDA. This pin must be connected to the corresponding PLL_VDDA through an
RC filter circuit, as shown in Figure 1, page 5. For more information about unused pins, see
Figure 4, page 14. For more information about unused pins, see Figure 4, page 14
• CCC_xyz_PLL_VSSA: This pin provides the internal PLL current return path for
CCC_xyz_PLL_VDDA. This pin must be connected to the corresponding PLL_VDDA through an RC
filter circuit, as shown in Figure 1, page 5. For more information about unused pins, see Figure 4,
page 14.
• MSS/HPMS_xDDR_PLL_VSSA: This pin provides the internal PLL current return path for
MSS/HPMS_xDDR_PLL_VDDA. This pin must be connected to the corresponding PLL_VDDA
through an RC filter circuit, as shown in Figure 1, page 5. For more information about unused pins,
see Figure 4, page 14.
For the device-package combinations listed in the following table, the SERDES_x_VDD pins are shorted
with VDD pins inside the package substrate to free up the package pins.
For detailed pin descriptions, see DS0115: SmartFusion2 Pin Descriptions Datasheet
or DS0124:
IGLOO2 Pin Descriptions Datasheet.
2.2.1 Power Supply Decoupling
To reduce any potential fluctuation on the power supply lines, decoupling capacitors, bypass capacitors,
and other power supply filtering techniques must be used.
To save board space, fewer, larger-value bulk capacitors can be used instead of a large number of
smaller capacitors. However, care must be taken to ensure that the electrical characteristics of the
consolidated capacitors (ESR and ESL) match those of the parallel combination of the recommended
capacitors.
Table 1 • Device-Package Combinations Without SERDES_x_VDD Pin
Device Package
M2S025T, M2GL025T FCS325
M2S050T(S), M2GL050T(S) FCS325
M2S060T(S), M2GL060T(S) FCS325
M2S90T(S), M2GL90T(S) FCS325
M2S10T(S), M2GL010T(S) VF256
M2S025TS, M2S025T, M2GL025TS,
M2GL025T
VF256
M2S150T(S), M2GL150T(S) FCV484
M2S150TS, M2S150T M2GL150TS,
M2GL150T
FCS536
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