Layout Guidelines for SmartFusion2- and IGLOO2-Based Board Design
AC393 Application Note Revision 14.0 46
3.4 DDR
Some of the variants support the fabric DDR (FDDR) and microcontroller subsystem DDR (MDDR) and
some variants support only FDDR in SmartFusion2. Refer datasheet to see on which bank DDR is
supported on each particular device. The layout guidelines of the respective VDDIO should be followed.
Apart from that, it requires VREF voltage for an internal reference. Noise on VREF impacts the read
performance of SmartFusion2/IGLOO2 devices. VREF lines should not be routed near the aggressive
nets or switching power supplies. For more information about DDR memory layout guidelines, see the
Micron DDR3 Memory Layout Guidelines. The VDDIO guidelines should be followed for DDR bank
VDDIO. This section explains the guidelines to be used for VREF.
3.4.1 Component Placement
3.4.1.1 VREF
• The bypass capacitor (10 µF) should be placed near, or at the edge of the device if possible.
• All decoupling capacitors (0.1 µF and 0.01 µF) should be 0402 or of a smaller package size as they
are required to be mounted on the reverse side of the board. They should be fit between the
adjacent vias of the BGA package pins. These decoupling capacitors are selected to have a low
impedance over the operating frequency and temperature range.
• The capacitor pad to via trace should be as small as possible. Figure 24, page 39 shows how these
capacitors are mounted. Microsemi recommends keeping the capacitor pad directly on the
corresponding vias.
3.4.1.2 VDDIO
• The bypass capacitors (47 µF and 22 µF) should be placed near, or at the edge of the device if
possible.
• All decoupling capacitors (0.1 µF and 0.01 µF) should be 0402 or of a smaller package size as they
are required to be mounted on the reverse side of the board. They should be fit between the
adjacent vias of the BGA package pins. These decoupling capacitors are selected to have a low
impedance over the operating frequency and temperature range.
• The capacitor pad to via trace should be as small as possible. Figure 24, page 39 shows how these
capacitors are mounted. The capacitors can also be mounted directly on the pad available on the
vias.
3.4.2 Plane Layout
3.4.2.1 VREF
Noise on VREF impacts the read performance of SmartFusion2/IGLOO2 devices. The VREF lines
should be routed with no aggressive net or switching power supply nearby. Even the current is low, VREF
should not be routed as trace as it is very susceptible to noise.
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