Microsemi IGLOO2 - I;O Glitch During Power-Down; Table 4 I;O Glitch During Power-Up; Table 5 I;O Glitch During Power-Down

Board Design Guidelines for SmartFusion2 SoC and IGLOO2 FPGAs
AC393 Application Note Revision 14.0 11
Recommendation: Glitches were observed in all the power-up cases. In most cases, it was not a true
glitch, but simply VDDI to pad capacitive source-drain coupling as the supply charges up. The glitch
could not be avoided under any ramp case scenario. The Glitch occurred for a maximum duration of 500
µs approximatively.
To remove the glitch, use an external 10 kΩ pull-down resistor.
2.3.2 I/O Glitch During Power-Down
The following table lists the I/O glitch observations during power-down found during internal testing.
Case 9 Output
driving
high
VPP and DEVRSTB
are constant at 3.3V;
VDD and VDDI are
ramped up
simultaneously
Yes
(less
amplitude
~560mV)
No glitch observed
Case 10 VPP, DEVRSTB,
and VDDI are
constant at
respective nominal
voltages; VDD is
ramped up
Yes
(less
amplitude
~296mV)
No glitch observed
Table 5 • I/O Glitch During Power-Down
Test Case Output State Test Condition Glitch Observed Comments
Case 1 Output driving
low
VPP and DEVRSTB are
constant 3.3V; VDD and
VDDI are ramped down
No -
Case 2 VPP and DEVRSTB are
ramped down; VDD and
VDDI are constant
Yes
(glitch amplitude ~1.53V)
From case 2 & 3
glitch(2V) is mainly due
to DEVRSTB
Case 3 DEVRSTB is ramped
down;
VPP, VDD, and VDDI are
constant
Yes
(glitch amplitude ~2.03V)
Case 4 Output driving
high
DEVRSTB is ramped up;
VPP, VDD, and VDDI are
constant
No -
Case 5 DEVRSTB is ramped
down;
VPP, VDD, and VDDI are
constant
No -
Case 6 Output tri-
stated
DEVRSTB is ramped up;
VPP, VDD, and VDDI are
constant
No -
Case 7 DEVRSTB is ramped
down;
VPP, VDD, and VDDI are
constant
Yes
(glitch amplitude ~1.75V)
-
Table 4 • I/O Glitch during Power-up (continued)
Test
Case Output Test Condition
Glitch
observed
(Yes or No) Comments
Observation with
10 KΩ Pull-Down
Resistor