Revision History
AC393 Application Note Revision 14.0 1
1 Revision History
The revision history describes the changes that were implemented in the document. The changes are
listed by revision, starting with the current publication.
1.1 Revision 14.0
The following is a summary of changes made in revision 14.0 of this document.
• Information about I/O glitches during power-up, power-down, and on blank devices was updated.
For more information, see I/O Glitch, page 9.
• A figure was added to illustrate SPI master mode programming. For more information, see SPI
Master Programming, page 24.
• Information about simultaneous switching noise support was added. For more information, see
Simultaneous Switching Noise, page 37.
• The design checklist from CL0034: SmartFusion2/IGLOO2 Hardware Board Design Checklist was
merged into this document.
• List of device-package combinations that do not have SERDES_x_VDD pins was added. For more
information, see Table 1, page 6.
• Design checklist was added in Board Design and Layout Checklist, page 82.
• Information about the de-coupling capacitor and SmartFusion2/IGLOO2 placement
was added in Component Placement, page 39.
• Figures were updated in LPDDR and DDR2 Design, page 30 and DDR3 Guidelines, page 32.
1.2 Revision 13.0
The following is a summary of changes made in revision 13.0 of this document.
• Updated Figure 4, page 14, Figure 17, page 31, Figure 18, page 32, Figure 19, page 33, and
Figure 20, page 33.
• Updated Table 6, page 15, Table 7, page 16, Table 8, page 16, Table 9, page 17, and Table 17,
page 29.
• AC408: Creating Schematic Symbols using Cadence OrCAD Capture CIS for SmartFusion2 and
IGLOO2 Designs is merged with this document.
1.3 Revision 12.0
The following is a summary of changes made in revision 12.0 of this document.
• Recommended bank supplies are updated for the FG484 package. See Table 7, page 16.
• Recommended bank supplies are updated for VF400 and FCS325 Packages. See Table 8, page 16.
• Recommended bank supplies are updated for VF256 and TQ144 Packages. See Table 9, page 17.
• Added a note about DQ pins that all 4- and 8-bit pins are interchangeable in LPDDR, DDR2, and
DDR3 memories. See Figure 17, page 31.
• Added that the SERDES_x_L[01/23]_VDDAPLL pin supports only 2.5 V, and removed 1.2 V
references from all occurrences. For more information, see Figure 1, page 5 and Table 19, page 35.
• AC394: Layout Guidelines for SmartFusion2- and IGLOO2-Based Board Design was added as a
part of Board Design guidelines itself.
1.4 Revision 11.0
The following is a summary of changes made in revision 11.0 of this document.
• The filter circuit for SERDES_x_VDD was removed. Even if it was used in the board design
previously, it does not affect the functionality of the board. See Figure 1, page 5.
• Information about VDDI2 was updated. See Table 8, page 16 and Table 9, page 17.
• Information about reset circuit was updated. see Reset Circuit, page 21.
• Changed the document to the new template.
To Next Page
Loading...
