Microsemi IGLOO2 - Layout Checklist; Table 24 Layout Checklist

Board Design and Layout Checklist
AC393 Application Note Revision 14.0 89
5.3 Layout Checklist
The following table lists the layout checks.
Table 24 • Layout Checklist
S.No. Description Yes/No
Power
1. Are 0402 or lesser size capacitors used for all decaps (less than value?)
2. Are power supply filters implemented on SERDES_x_VDDAPL, and SERDES_x_PLL_VDDA as
shown in the Figure 28, page 42 and Figure 40, page 50 respectively?
3. Is precision 1.2 K resistor between SERDES_x_REFRET and SERDES_x_REXT used?
4. Are placement and layout guidelines followed for 1.2 K resistor?
5. Is the target impedance met on all power planes?
6. Are VREF planes for DDRx reference supply isolated from the noisy planes?
7. Are enough number of decoupling capacitors used for DDRx core and VTT supply? For more
information about DDRx core and VTT supply, see Board Design Guidelines for SmartFusion2 SoC
and IGLOO2 FPGAs, page 4.
8. Is one 0.1 µF cap for two VTT termination resistors used for DDRx?
9. Is enough plane width provided for VTT plane?
DDR3
10. Are length match recommendations followed according to the DDR3 guidelines?
SerDes
11. Are length match recommendations followed according to the SerDes guidelines?
12. Are the DC blocking capacitors used for SerDes TX and if required on RX lines?
13. Is tight controlled impedance maintained along the SerDes traces?
14. Are differential vias well designed to match SerDes trace impedance?
15. Are DC blocking capacitor pads designed to match SerDes trace impedance?
Dielectric Material
16. Is proper PCB material selected for critical layers?