Board Design and Layout Checklist
AC393 Application Note Revision 14.0 88
49. Provide a sufficient number of ground pins for board-to-board connectors to
ensure signal integrity (SI) across connectors.
Dense board-to-board connectors may cause severe cross-talk problems. The
severity of crosstalk depends on the frequency of the signal and the spacing
between signal pins on the connectors. (The number of ground pins may be
obtained after performing SI analysis.) The severity can be reduced by
providing ground pins between signal pins.
50. Use proper voltage-level translator devices for interfacing higher-operating-
voltage devices with lower-operating-voltage devices.
51. Perform timing analysis of all components, taking into consideration the delays
introduced by buffers in the data, address, or control paths.
52. Perform signal integrity analysis (pre-layout and post-layout) for all critical
interfaces and all types of I/Os using input/output buffer information
specification (IBIS).
53. Analyze the design for simultaneous switching noise (SSN) problems:
– Use differential I/O standards and lower-voltage standards for high switching
I/Os.
– Reduce the number of simultaneously switching output pins within each
bank.
– Reduce the number of pins that switch voltage levels at the same time.
– Use lower drive strengths for high switching I/Os. The default drive strength
setting might be higher than the design requirement.
– Spread output pins across multiple banks if possible.
– If bank usage is substantially below 100%, spread the switching I/Os evenly
throughout the bank to reduce the number of aggressors in a given area to
reduce SSN.
– Separate simultaneously switching pins from input pins that are susceptible to
SSN.
54. Place important clock and asynchronous control signals near ground signals
and away from large switching buses.
55. I/O Pin Assignment
Use a spreadsheet to capture the list of design I/Os. Microsemi provides
detailed pinout information that can be downloaded from the website and
customized to store the pinout information for specific designs.
Pinout details for various packages with different densities are available on the
following pages:
SmartFusion2 SoC FPGA Documentation
IGLOO2 FGPA Documentation
56. Check if there are any incompatible I/O standards combined in the same bank.
57. Check if there are two interfaces with different voltage standards in the same
bank.
58. See the bank location diagrams in the IGLOO2 Pin Descriptions /
SmartFusion2 Pin Descriptions documents to assess the preliminary
placement of major components on PCB.
Table 23 • Design Checklist (continued)
S.No. Checklist Yes/No
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