Board Design and Layout Checklist
AC393 Application Note Revision 14.0 87
DDR Interface
37. DDR Interface
Short DDR TMATCH IN to DDR TMATCH OUT.
Short DDR TMATCH ECC IN to DDR TMATCH ECC OUT.
VDDI bank supply should be powered as per the application:
– For LPDDR - VDDI should be 1.8 V
– For DDR2- VDDI should be 1.8 V
– For DDR3- VDDI should be 1.5 V
DDR impedance calibration pin should be pulled down with the following
resistors:
– For LPDDR- 150 Ω
– For DDR2- 150 Ω
– For DDR3- 240 Ω
Though calibration is not required, it is recommended to use corresponding
resistor placeholder to connect the pin to the ground with or without a resistor.
All data and data strobe signals have internal ODT settings, which can be
enabled through the Libero software.
Hot-swapping and Cold-Sparing
38. All user I/Os have internal clamp diode control circuitry for protection.
MSIO pins (except PCI 3.3 V standard) support the hot-swapping and cold-
sparing operations. MSIOD and DDRIO pins do not support hot swapping and
cold-sparing operations
General Guidelines
39. For all MSIO, MSIOD, and DDRIO, a weak internal pull-up resistor is available.
In unused condition, these pins can be left floating.
40. MSIOD and DDRIO support a maximum of 2.5 V. MSIO supports maximum of
3.3 V.
41. There is one MSI special pin (MSIO) available that can be used as input only.
This pin is differentially paired with FLASH_GOLDEN_N, which is always input
only.
For more information, see the following documents:
– IGLOO2 Pin Descriptions
– SmartFusion2 Pin Descriptions
42. One internal signal can be allocated for probing (for example, towards the
oscilloscope feature). The two live probe I/O cells are dual-purpose. They can
be used for the live probe functionality or used as user I/Os (MSIO).
43. MSS peripherals (SPI, I2C, USB, and UART) are available.
44. Provide pull-up resistors for all open-collector or open-drain pins, even if a pin
is not used.
45. Provide separate pull-down resistors for all used open-emitter or open-source
pins.
46. Enable internal pull-up/pull-down resistor option for all tri-state nets through the
Libero tool.
47. Ensure that all the critical signals on the board are terminated properly.
48. Terminate the unused interface signals properly to avoid metastability and
electromagnetic interference (EMI)/electromagnetic compatibility (EMC)
problems.
Table 23 • Design Checklist (continued)
S.No. Checklist Yes/No
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