Board Design and Layout Checklist
AC393 Application Note Revision 14.0 86
Programming
34. The device can be programmed either through JTAG interface or serial
peripheral interface (SPI) interface.
FLASH_GOLDEN_N
If pulled low, it indicates that the device is to be re-programmed from an image
in the external SPI flash attached through the SPI interface. If pulled high, the
SPI is put in slave mode.
Add a 10kΩ external pull-up resistor to VDDI.
Some devices do not support the FLASH_GOLDEN_N pin. Check the PPAT
spreadsheets available on the following Microsemi webpages:
SmartFusion2 SoC FPGA Documentation
IGLOO2 FGPA Documentation
For more information about dedicated pins including Flash_GOLDEN_N, see
Table 16, page 25.
Configuring Pins in Open Drain Using Tri-state Buffer
35. To configure fabric pins in open-drain mode, the tristate buffer input pin must
always be grounded, and the I/O pin of the FPGA must be connected to the
active-low enable pin of the buffer. For more information, see Figure 22,
page 36.
SerDes Pins
36. Dedicated I/O are available for the SerDes high-speed serial interface, which
supports the PCIe, SGMII, XAUI, and JESD204B protocols.
SERDES Clock: 100 MHz to 160 MHz LVDS source.
The SerDes reference clock pins have internal on-die termination (ODT)
settings. These settings can be enabled through the Libero software.
The reference clock source (differential clock oscillator) is selected based on
many parameters such as frequency range, output voltage swing, jitter
(deterministic, random, and peak-to-peak), rise and fall times, supply voltage
and current, noise specification, duty cycle, duty cycle tolerance, and frequency
stability.
An example clock source can be the CCLD-033- LVDS clock oscillator.
SerDes clock requirements for different protocols are as follows:
– PCIe: 100 MHz
– XAUI: 156.25 MHz
– SGMII: 125 MHz
– EPCS: 125 MHz
– SERDES TXD: The transmit pair must alone have AC-coupling capacitors
near the SmartFusion2/IGLOO2 device. AC-coupling capacitors of 75-200 nF
are required for link detection. If the SerDes unit is unused, these pins must
remain floating (DNC).
– SERDES RXD: The receive pair must have AC-coupling capacitors near the
endpoint device. If the SerDes unit unused, these pins must always be
connected to ground.
For more information about SerDes, see SerDes, page 41.
Table 23 • Design Checklist (continued)
S.No. Checklist Yes/No
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