Board Design Guidelines for SmartFusion2 SoC and IGLOO2 FPGAs
AC393 Application Note Revision 14.0 18
SmartFusion2/IGLOO2 device reset can be activated either directly through an external DEVRST_N pin
or indirectly through the tamper macro IP. When the device reset is asserted, the system controller
immediately puts the FPGA core in inactive state. During this operation, depending on the board design
layout and decoupling capacitors used, there may be additional surge current on the VDD power rail. The
additional surge current has no effect on device reliability. This surge current is for a very short duration
and is normally handled by bulk decoupling capacitors on the power plane in a typical system. In cases
where Microsemi-recommended board design guidelines cannot be implemented for decoupling
capacitors for VDD (due to limited board spacing or other reasons), higher-than-expected surge current
may occur during device reset.
The following table provides characterized surge current data for VDD during DEVRST_N assertion.
This data represents the worst-case condition with no decoupling capacitors on the board.
However, the surge current data in the preceding table does not represent a typical system. To illustrate
this, surge current during device reset was measured at room temperature separately for the M2S090
security evaluation kit and the M2S150 advanced development kit. These kits have decoupling capacitors
according to the Microsemi-recommended board design guidelines. The following table lists the surge
currents observed on the M2S090 security evaluation kit and the M2S150 advanced development kit.
The surge current values were found to be within acceptable limits.
The digest check system service performs on-chip NVM data integrity check on SmartFusion2 devices.
The use of system services by digest check may cause additional surge current on VDD. For more
information on digest check service, see the UG0450: SmartFusion2 SoC and IGLOO2 FPGA System
Controller User Guide.
Table 10 • Surge Current on VDD during DEVRST_N Assertion (No Decoupling Capacitors on Board)
Device
Width of Surge at
50% of Pulse (µS)
Surge Current on VDD
Units0 °C to 85 °C –40 °C to 100 °C –55 °C to 125 °C
M2S005/M2GL005 2 0.5 0.6 0.6 A
M2S010/M2GL010 3 0.9 0.9 0.9 A
M2S025/M2GL025 6 1.7 1.7 1.7 A
M2S050/M2GL050 12 3.2 3.2 3.2 A
M2S060/M2GL060 12 3.2 3.2 3.2 A
M2S090/M2GL090 22 4.4 4.6 4.6 A
M2S150/M2GL150 42 7.0 7.3 7.3 A
Table 11 • M2S090 and M2S150 Surge Current During DEVRST_N Assertion (With Decoupling
Capacitors on Board)
Kit
Width of Surge at 50%
of Pulse Surge Current
M2S090 Security Evaluation Kit 5 µs 150 mA
M2S150 Advanced Development Kit 40 µs 1.5 A
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