Microsemi IGLOO2 - MDDR;FDDR Impedance Calibration; Table 17 LPDDR;DDR2;DDR3 Parameters

Board Design Guidelines for SmartFusion2 SoC and IGLOO2 FPGAs
AC393 Application Note Revision 14.0 29
The following table lists the differences between LPDDR, DDR2, and DDR3.
One major difference between DDR2 and DDR3 SDRAM is the use of data leveling. To improve signal
integrity and support higher frequency operations, a fly-by termination scheme is used with the clocks,
command, and address bus signals. Fly-by termination reduces simultaneous switching noise by
deliberately causing flight-time skew between the data strobes at every DDR3 chip. Fly-by termination
requires controllers to compensate for this skew by adjusting the timing per byte lane. To obtain length
matching, short TMATCH_OUT to TMATCH_IN with the shortest loop.
For more information about DDR memories, refer to the following documents:
• JESD209B-JEDEC STANDARD—Low Power Double Data Rate (LPDDR) SDRAM Standard
• JESD79-2F-JEDEC STANDARD—DDR2 SDRAM Specification
• JESD79-3F-JEDEC STANDARD—DDR3 SDRAM Standard
2.9.1 MDDR/FDDR Impedance Calibration
The MDDR and FDDR have a DDRIO calibration block. DDRIO can use fixed impedance calibration for
different drive strengths, and these values can be programmed using the Libero SoC software for the
selected I/O standard.
Before initiating DDRIO impedance calibration, either of the following must be done:
• Power sequencing, where the DDRIO bank VDDIx supply must be up and stable before VDD core
supply.
• DDRIO re-calibration through the APB interface after DDRIO- VDDIx and VDD are up and stable.
For more information on impedance calibration, see the UG0445: SmartFusion2 SoC and IGLOO2
FPGA Fabric User Guide.
Table 17 • LPDDR/DDR2/DDR3 Parameters
Parameter LPDDR DDR2 DDR3
VDDQ 1.8 V 1.8 V 1.5 V
VTT, VREF 0.9 V 0.75 V
Clock, address, and command
(CAC) layout
Asymmetrical tree branch Symmetrical tree
branch
Daisy chained (fly-by)
Data strobe Single-ended Differential Differential
ODT None Static Dynamic
Match Addr/CMD/Ctrl to clock
tightly
Yes Yes Yes
Match DQ/DM/DQS tightly Yes Yes Yes
Match DQS to clock loosely Yes Yes Not required
Interface LVCMOS_18 or SSTL18 for
LPDDR1
SSTL_18 SSTL_15
Impedance Calibration LVCMOS18 - Not required
SSTL18 - Required
150_1% 240_1%