Microsemi IGLOO2 - JTAG Programming; Programming Interface Overview

Board Design Guidelines for SmartFusion2 SoC and IGLOO2 FPGAs
AC393 Application Note Revision 14.0 10
Table 4 • I/O Glitch during Power-up
Test
Case Output Test Condition
Glitch
observed
(Yes or No) Comments
Observation with
10 KΩ Pull-Down
Resistor
Case 1 Output
driving
low
VPP and DEVRSTB
are constant at 3.3V;
VDD & VDDI are
ramped up
Simultaneously
Yes
(less
amplitude
~480mV)
- No glitch observed
Case 2 VPP and DEVRSTB
are ramped up;
VDD and VDDI are
constant at
respective nominal
voltages
Yes
(less
amplitude
~70mV)
From case 2
& 3
glitch(70mV)
is mainly due
to VPP
No glitch observed
Case 3 DEVRSTB is
ramped up;
VPP,VDD, and VDDI
are constant at
respective nominal
voltages
Yes
(less
amplitude
~70mV)
Case 4 VPP and DEVRSTB
are constant 3.3V;
VDD and VDDI are
ramped up
(VDD Leading
VDDI)
Yes
(less
amplitude
~532mV)
No glitch observed
Case 5 VPP and DEVRSTB
are constant 3.3V;
VDD and VDDI are
ramped up (VDD
Lagging VDDI)
Yes
(less
amplitude
~448mV)
No glitch observed
Case 6 VPP, DEVRSTB,
and VDDI are
constant at
respective nominal
voltages; VDD is
ramped up
Yes
(less
amplitude
~296mV
with Bank4
and
~136mV
with Bank0)
From this
case glitch is
mainly due to
VDD ramp
up.
It is
inconsistent
No glitch observed
Case 7 VPP, DEVRSTB,
and VDD are
constant at
respective nominal
voltages; VDDI is
ramped up
Yes
(less
amplitude
~144mV)
No glitch observed
Case 8 VPP = 3.3V;
DEVRSTB = 0V
VDD and VDDI are
ramped up
simultaneously
Yes
(less
amplitude
~480mV)
No glitch observed