Layout Guidelines for SmartFusion2- and IGLOO2-Based Board Design
AC393 Application Note Revision 14.0 64
3.10.2.1 Data Group Signal Routing
• The data signals should not be over the split planes.
• The reference plane for data signals should be GND plane and should be contiguous between
memory and SmartFusion2/IGLOO2.
• Traces should not be routed at the edge of the reference plane and over via anti pads.
• When routing the data signals, the longest signals should be routed first, this allows to adjust the
length for the short length signals, when routing data signals.
• Serpentine routing should be used to adjust the data group signals to meet this requirement.
• The DQS signal should be routed along with associated data byte lane on the same critical layer
with the same via count. Using more than three vias in the connection between the FPGA controller
and memory device should be avoided.
• The impedance for the data traces depends on the stack-up and the trace width. There are options
to select the impedance based on the stack-up and trace width.
• 40
Ω impedance, which requires wide traces (~7 to 8 mils). This gives the less cross talk and
less spacing between the traces (~2x). Spacing between non-DDR signals and DDR signals
should be ~4x.
• 50
Ω impedance, which requires smaller trace width (~4 to 6mils). This requires more spacing
between the traces (~3x). Spacing between non DDR signals and DDR signals should be ~4x.
• All data lanes should be matched to within 0.5 inch.
• Within the data lane, each trace should be matched to within ±10mils of its respective data strobe
• The DQS and DQS# need to be matched within +/- 5mils.
• Differential impedance should be between 75 to 100 Ω.
• Differential traces adjacent to noisy signals or clock chips should be avoided.
• Spacing between differential lines should be 5 to 8 mils.
3.10.2.2 Address, Control, Command, and Clock Routing
• These signals should be routed in the fly-by topology and terminated with appropriate termination
resistor at the end of the signals. The resistor termination should not have a stub longer than 600
mil.
• The impedance for the trace depends on the stack-up and trace width. There are options to select
the impedance based on the stack-up and trace width:
• 40
Ω impedance, which requires wide traces (~7 to 8 mils). This gives the less cross talk and
less spacing between the traces (~2x). Spacing between non DDR signals and DDR signals
should be ~4x.
• 50
Ω impedance, which requires smaller trace width (~4 to 6mils). This requires more spacing
between the traces (~3x). Spacing between non DDR signals and DDR signals should be ~4w
to avoid crosstalk issues.
• Address and control signals can be referenced to a power plane if a ground plane is not
available. The power plane should be related to the memory interface. However, a ground
reference is preferred. Address and control signals should be kept on a different routing layer
from DQ, DQS, and DM to isolate crosstalk between the signals.
3.10.2.3 Clock
• Clock signals are routed differentially, and the length matches between traces should be
+/- 5 mils.
• It should be referenced to ground plane.
• The space between clock and other signals should be 25 mils.
• One clock signal is routed per rank of the DIMM, that is, one clock for single-ranked DIMM, two clock
signals for the dual ranked DIMM. For non-DIMM systems, the differential terminations used by the
CK/CK# pair must be located as close as possible to the memory.
• If more than one CS is used, the same clock to DQS skew should be applied to all CS.
• Address/control signals and the associated CK and CK# differential FPGA clock should be routed
with trace matching ±100 mil.
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